RX21A_15 Datasheet, PDF (94/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
5. Electrical Characteristics
Table 5.33 Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = AVCC0 = AVCCA = 1.8 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
T_a = –40 to +105°C
When high-drive output is selected by the drive capacity register while 1.8 V ≤ VCC < 2.7 V
Item
Symbol
Min.
Max.
Unit*¹ Test Conditions
Simple SCK clock cycle output (master)
SPI
SCK clock cycle input (slave)
t_SPcyc
4
65536
t_Pcyc C = 30 pF
6
65536
Figure 5.49
SCK clock high pulse width
t_SPCKWH
0.4
SCK clock low pulse width
t_SPCKWL
0.4
SCK clock rise/fall time
t_SPCKr, t_SPCKf
—
Data input setup time
2.7 V ≤ VCC ≤ 3.6 V
t_SU
65
(Master)
1.8 V ≤ VCC < 2.7 V
75
Data input setup time (Slave)
40
0.6
t_SPcyc
0.6
t_SPcyc
20
ns
—
ns C = 30 pF
—
Figure 5.50 to
Figure 5.53
—
Data input hold time
SS input setup time
SS input hold time
Data output delay time (Master)
Data output delay time
(Slave)
2.7 V ≤ VCC ≤ 3.6 V
1.8 V ≤ VCC < 2.7 V
t_H
t_LEAD
t_LAG
t_OD
40
—
ns
6
—
t_Pcyc
6
—
t_Pcyc
—
40
ns
—
65
—
85
Data output hold time
t_OH
–10
Data rise/fall time
t_Dr, t_Df
—
SS input rise/fall time
t_SSLr, t_SSLf
—
Slave access time
t_SA
—
Slave output release time
2.7 V ≤ VCC ≤ 3.6 V
t_REL
—
1.8 V ≤ VCC < 2.7 V
—
—
ns
20
ns
20
ns
5
t_Pcyc C = 30 pF
5
t_Pcyc
Figure 5.52 and
Figure 5.53
6
Note 1. t_Pcyc: PCLK cycle
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
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