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RX21A_15 Datasheet, PDF (79/132 Pages) Renesas Technology Corp – Renesas MCUs
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RX21A Group
5.3 AC Characteristics
5. Electrical Characteristics
Table 5.19 Operation Frequency Value (High-Speed Operating Mode)
Conditions: VCC = AVCC0 = AVCCA = 2.7 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
Ta = –40 to +105°C
VCC
Item
Symbol
Unit
2.7 to 3.6 V
Maximum operating System clock (ICLK)
fmax
50
MHz
frequency
FlashIF clock (FCLK)*1
25
Peripheral module clock (PCLKA)
50
Peripheral module clock (PCLKB)
25
Peripheral module clock (PCLKC)*2
25
Peripheral module clock (PCLKD)*3
25
Note 1. The lower-limit frequency of FCLK is 4 MHz during programming or erasing of the flash memory.
Note 2. The frequency of PCLKC is 25 MHz when the ∆Σ A/D converter is in use.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Table 5.20 Operation Frequency Value (Medium-Speed Operating Mode 1A)
Conditions: VCC = AVCC0 = AVCCA = 1.8 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
Ta = –40 to +105°C
VCC
Item
Symbol
Unit
1.8 to 2.7 V
2.7 to 3.6 V
Maximum operating
frequency
System clock (ICLK)
FlashIF clock (FCLK)*1
fmax
25
25
25
MHz
25
Peripheral module clock (PCLKA)
25
25
Peripheral module clock (PCLKB)
25
25
Peripheral module clock (PCLKC)*2
25
25
Peripheral module clock (PCLKD)*3
25
25
Note 1. The VCC is 2.7 to 3.6 V and the lower-limit frequency of FCLK is 4 MHz during programming or erasing of the flash memory.
Note 2. The frequency of PCLKC is 25 MHz when the ∆Σ A/D converter is in use.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Table 5.21 Operation Frequency Value (Medium-Speed Operating Mode 1B)
Conditions: VCC = AVCC0 = AVCCA = 1.8 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
Ta = –40 to +105°C
VCC
Item
Symbol
Unit
1.8 to 2.7 V
2.7 to 3.6 V
Maximum operating
frequency
System clock (ICLK)
FlashIF clock (FCLK)*1
fmax
25
25
25
MHz
25
Peripheral module clock (PCLKA)
25
25
Peripheral module clock (PCLKB)
25
25
Peripheral module clock (PCLKC)*2
25
25
Peripheral module clock (PCLKD)*3
25
25
Note 1. The lower-limit frequency of FCLK is 4 MHz during programming or erasing of the flash memory.
Note 2. The frequency of PCLKC is 25 MHz when the ∆Σ A/D converter is in use.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 79 of 132
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