RX21A_15 Datasheet, PDF (91/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
5.4.4
Timing of On-Chip Peripheral Modules
5. Electrical Characteristics
Table 5.30 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = AVCCA = 1.8 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit*¹
Test
Conditions
I/O ports Input data pulse width
MTU
Input capture input pulse width
t_PRW
1.5
Single-edge setting
t_TICW
1.5
Both-edge setting
2.5
—
t_Pcyc Figure 5.41
—
t_Pcyc Figure 5.42
—
Timer clock pulse width
Single-edge setting
t_TCKWH,
1.5
Both-edge setting
t_TCKWL
2.5
—
t_Pcyc Figure 5.43
—
Phase counting
mode
2.5
—
POE
8-bit
timer
POE# input pulse width
Timer clock pulse width
t_POEW
1.5
Single-edge setting t_TMCWH,
1.5
Both-edge setting
t_TMCWL
2.5
—
t_Pcyc Figure 5.44
—
t_Pcyc Figure 5.45
—
A/D
Trigger input pulse width
converter
t_TRGW
1.5
—
t_Pcyc Figure 5.48
CAC
CACREF input pulse width
t_Pcyc ≤ t_cac*²
t_Pcyc > t_cac*²
t_CACREF 4.5 t_cac + 3 t_Pcyc
—
ns
5 t_cac + 6.5 t_Pcyc
Note 1. t_Pcyc: PCLK cycle
Note 2. t_cac: CAC count clock source cycle
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 91 of 132