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RX21A_15 Datasheet, PDF (120/132 Pages) Renesas Technology Corp – Renesas MCUs
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RX21A Group
5.12 ROM (Flash Memory for Code Storage) Characteristics
5. Electrical Characteristics
Table 5.47 ROM (Flash Memory for Code Storage) Characteristics (1)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Reprogramming/erasure cycle*1
Data hold time
After 1000 times
of NPEC
After 10000 times
of NPEC
NPEC
tDRP
10000
30*2
1*2
—
—
Times
—
—
Year Ta = +85°C
—
—
Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 128-byte programming is
performed 16 times for different addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is
counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Note 2. This result is obtained from reliability testing.
Table 5.48 ROM (Flash Memory for Code Storage) Characteristics (2)
: high-speed operating mode, medium-speed operating modes 1A and 2A
Conditions: VCC = AVCC0 = AVCCA = 2.7 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
FCLK = 4 MHz
FCLK = 25 MHz
Item
Symbol
Unit
Min.
Typ. Max.
Min.
Typ. Max.
Programming time
2 bytes
when NPEC ≤ 100 times 8 bytes
128 bytes
Programming time
2 bytes
when NPEC > 100 times 8 bytes
128 bytes
Erasure time
2 Kbytes
when NPEC ≤ 100 times
Erasure time
2 Kbytes
when NPEC > 100 times
Suspend delay time during programming
(in programming/erasure priority mode)
tP2
tP8
tP128
tP2
tP8
tP128
tE2K
tE2K
tSPD
—
0.19 4.3
—
0.12 2.1 ms
—
0.19 4.4
—
0.12 2.1
—
0.67 10.7
—
0.42 5.0
—
0.23 5.3
—
0.15 2.6 ms
—
0.23 5.4
—
0.15 2.6
—
0.80 13.2
—
0.50 6.3
—
13.0 92.8
—
10.6 31.6 ms
—
15.9 176.9
—
13.0 64.7 ms
—
—
0.9
—
— 0.804 ms
First suspend delay time during
tSPSD1
—
programming (in suspend priority mode)
—
220
—
—
124 μs
Second suspend delay time during
tSPSD2
—
—
0.9
—
— 0.804 ms
programming (in suspend priority mode)
Suspend delay time during erasing
tSED
—
—
0.9
—
— 0.804 ms
(in programming/erasure priority mode)
First suspend delay time during erasing
tSESD1
—
(in suspend priority mode)
—
220
—
—
124 μs
Second suspend delay time during erasing tSESD2
—
—
0.9
—
— 0.804 ms
(in suspend priority mode)
FCU reset time
tFCUR 20 μs or longer —
and FCLK × 6
or greater
— 20 μs or longer —
and FCLK × 6
or greater
—
μs
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 120 of 132
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