RX21A_15 Datasheet, PDF (92/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
5. Electrical Characteristics
Table 5.31 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = AVCCA = 1.8 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
T_a = –40 to +105°C
When high-drive output is selected by the drive capacity register while 1.8 V ≤ VCC < 2.7 V
Item
Symbol
Min.
SCI
Input clock cycle
Asynchronous
Clock synchronous
t_Scyc
4
6
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
Asynchronous
Clock synchronous
t_SCKW
0.4
t_SCKr
—
t_SCKf
—
t_Scyc
16
4
Output clock pulse width
t_SCKW
0.4
Output clock rise time
t_SCKr
—
Output clock fall time
t_SCKf
—
Transmit data delay time
Clock synchronous (master)
t_TXD
—
Transmit data delay time
Clock synchronous (slave)
—
2.7 V ≤ VCC ≤ 3.6 V
Clock synchronous (slave)
—
1.8 V ≤ VCC < 2.7 V
Receive data setup time
Clock synchronous (master)
t_RXS
65
2.7 V ≤ VCC ≤ 3.6 V
Clock synchronous (master)
75
1.8 V ≤ VCC < 2.7 V
Clock synchronous (slave)
40
Receive data hold time
Clock synchronous
t_RXH
40
Max.
—
—
0.6
20
20
—
—
0.6
20
20
40
65
Unit*¹
t_Pcyc
Test
Conditions
C = 30 pF
Figure 5.46
t_Scyc
ns
ns
t_Pcyc
C = 30 pF
Figure 5.47
t_Scyc
ns
ns
ns
85
—
ns
—
—
—
ns
Note 1. t_Pcyc: PCLK cycle
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 92 of 132