RX21A_15 Datasheet, PDF(130/132 Page) Renesas Technology Corp

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RX21A_15 Datasheet, PDF (130/132 Pages) Renesas Technology Corp – Renesas MCUs

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RX21A Group

REVISION HISTORY

Classifications

- Items with Technical Update document number: Changes according to the corresponding issued Technical Update

- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued

Rev.

1.10

Date

Page

Description

Summary

2014.08.28 Features

LGA package, added

1. Overview

Table 1.1 Outline of Specifications: Package added

Table 1.1 Outline of Specifications: Note 2 added

Table 1.1 Outline of Specifications: Note 3 added

Table 1.2 Comparison of Functions for Different Packages, changed

Table 1.3 List of Products, changed

Table 1.3 List of Products: Note 1 added

Table 1.3 List of Products: Note, Note 2 added

Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type, changed

Table 1.4 Pin Functions: Realtime clock changed

Figure 1.6 Pin Assignments of the 100-Pin TFLGA (Upper Perspective View), added

23 to 25 Table 1.8 List of Pins and Pin Functions (100-Pin TFLGA), added

3. Address Space

Figure 3.1 Memory Map, changed

4. I/O Registers

54 to 55 Table 4.1 List of I/O Registers (Address Order): FEFF FAC0h to FEFF FBD3h added

5. Electrical Characteristics

Table 5.3 DC Characteristics (2)

Table 5.4 DC Characteristics (3), changed

Table 5.6 DC Characteristics (5), changed

Table 5.7 DC Characteristics (6), changed

Table 5.9 DC Characteristics (8), added

Table 5.10 DC Characteristics (9), changed

Table 5.11 DC Characteristics (10), changed

Table 5.14 DC Characteristics (13), changed

Table 5.15 Permissible Output Currents (1), changed

Table 5.16 Permissible Output Currents (2), added

Table 5.18 Output Values of Voltage (2), changed

Table 5.26 Clock Timing, changed

Table 5.26 Clock Timing: Note 5 changed

Figure 5.27 LOCO, IWDTCLK Clock Oscillation Start Timing, changed

Figure 5.35 Reset Input Timing at Power-On, changed

Table 5.33 Timing of On-Chip Peripheral Modules (4), changed

103

Table 5.36 âÎ£ A/D Conversion Characteristics, changed

104

Figure 5.55 Differential Input Amplitude, changed

108

Table 5.37 A/D Conversion Characteristics (1), changed

108

Figure 5.61 AVCC to VREFH0 Voltage Range, added

109

Table 5.39 A/D Conversion Characteristics (2), changed

111

Differential nonlinearity error (DNL), description changed

115

Table 5.44 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (1): Note1, Note2 changed

Appendix 1. Package Dimensions

128

Figure D. 100-Pin TFLGA (PTLG0100JA-A), added

Classification

TN-RX*-A072A/E

TN-RX*-A073A/E

TN-RX*-A072A/E

TN-RX*-A074A/E

TN-RX*-A097A/E

TN-RX*-A105A/E

TN-RX*-A097A/E

TN-RX*-A074A/E

TN-RX*-A105A/E

TN-RX*-A074A/E

TN-RX*-A073A/E

TN-RX*-A074A/E

TN-RX*-A072A/E

All trademarks and registered trademarks are the property of their respective owners.

R01DS0129EJ0110 Rev.1.10

Aug 28, 2014

Page 130 of 132

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