RX21A_15 Datasheet, PDF (2/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 shows the outline of the specifications and Table 1.2 shows the comparison of the functions of products in
different packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1 / 4)
Classification Module/Function
Description
CPU
CPU
 Maximum operating frequency: 50 MHz
 32-bit RX CPU
 Minimum instruction execution time: One instruction per state (cycle of the system clock)
 Address space: 4-Gbyte linear
 Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
 Basic instructions: 73
 DSP instructions: 9
 Addressing modes: 10
 Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32 x 32  64 bits
 On-chip divider: 32 / 32  32 bits
 Barrel shifter: 32 bits
 Memory protection unit (MPU)
Memory
ROM
 Capacity: 256 K/384 K/512 Kbytes
 50 MHz, no-wait memory access
 On-board programming: 3 types
RAM
 Capacity:32 K/64 Kbytes
 50 MHz, no-wait memory access
E2 DataFlash
 Capacity: 8 Kbytes
 Number of times for programming/erasing: 100,000
MCU operating mode
Single-chip mode
Clock
Clock generation circuit
 Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator
 Oscillation stop detection
 Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
 Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 50 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK):25 MHz (at max.)
The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 25 MHz (at
max.)
Reset
RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog
timer reset, deep software standby reset, and software reset
Voltage detection Voltage detection circuit
(LVDAa)
 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 2 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 9 levels
Low power
consumption
Low power consumption
facilities
 Module stop function
 Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode
Function for lower operating High-speed operating mode, middle-speed operating mode 1A, middle-speed operating mode 1B,
power consumption
middle-speed operating mode 2A, middle-speed operating mode 2B, low-speed operating mode 1, low-
speed operating mode 2
Interrupt
Interrupt controller (ICUb)
 Interrupt vectors: 122
 External interrupts: 9 (NMI and IRQ0 to IRQ7 pins)
 Non-maskable interrupts: 6 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, WDT interrupt, and IWDT interrupt)
 16 levels specifiable for the order of priority
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
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