RX21A_15 Datasheet, PDF (55/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (24 / 24)
Address
FEFF FB74h
FEFF FB78h
FEFF FB7Ch
FEFF FB80h
FEFF FB84h
FEFF FB88h
FEFF FB90h
FEFF FB94h
FEFF FB98h
FEFF FB9Ch
FEFF FBA0h
FEFF FBA4h
FEFF FBA8h
FEFF FBACh
FEFF FBB0h
FEFF FBB4h
FEFF FBB8h
FEFF FBBCh
FEFF FBD0h
Module
Symbol
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
Register Name
∆ΣA/D gain calibration data register 1 X4*³
∆ΣA/D gain calibration data register 2 X4*³
∆ΣA/D gain calibration data register 3 X4*³
∆ΣA/D gain calibration data register 4 X4*³
∆ΣA/D gain calibration data register 5 X4*³
∆ΣA/D gain calibration data register 6 X4*³
∆ΣA/D gain calibration data register 0 X8*³
∆ΣA/D gain calibration data register 1 X8*³
∆ΣA/D gain calibration data register 2 X8*³
∆ΣA/D gain calibration data register 3 X8*³
∆ΣA/D gain calibration data register 0 X16*³
∆ΣA/D gain calibration data register 1 X16*³
∆ΣA/D gain calibration data register 2 X16*³
∆ΣA/D gain calibration data register 3 X16*³
∆ΣA/D gain calibration data register 0 X32*³
∆ΣA/D gain calibration data register 1 X32*³
∆ΣA/D gain calibration data register 2 X32*³
∆ΣA/D gain calibration data register 3 X32*³
∆ΣA/D input impedance calibration data register*³
Register
Symbol
DSADG1X4
DSADG2X4
DSADG3X4
DSADG4X4
DSADG5X4
DSADG6X4
DSADG0X8
DSADG1X8
DSADG2X8
DSADG3X8
DSADG0X16
DSADG1X16
DSADG2X16
DSADG3X16
DSADG0X32
DSADG1X32
DSADG2X32
DSADG3X32
DSADIIC
Number of Access Cycles
Number Access ICLK 
of Bits Size
PCLK
ICLK <
PCLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
32
32
1ICLK
Note 1.
Note 2.
Note 3.
Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 24.4 lists register
allocation for 16-bit access.
Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMOCNTL register. Table 31.3 lists register
allocation for 16-bit access.
Only G version products have these registers.
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 55 of 132