NS16C2552 Datasheet, PDF (7/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

5.0 Pin Descriptions (Continued)
Signal
Name
DSR1
DSR2
DCD1
DCD2
RI1
RI2
MF1
MF2
Type
I
I
I
O
PLCC
Pin #
41
29
42
30
43
31
35
19
TQFP
Pin #
39
25
40
26
41
27
32
14
Description
UART Data-set-ready:
When low, DSR indicates that the remote link partner is ready to establish the
communications link. The DSR signal is a MODEM status input and can be read for
the appropriate channel in MSR[5]. This bit reflects the complement of the DSR
signal. MSR[1] indicates whether the DSR input has changed state since the previous
read of the MODEM Status Register.
Note: Whenever the DSR bit of the MSR changes state, an interrupt is generated if the MODEM Status
Interrupt is enabled.
UART Data-carrier-detect:
When low, DCD indicates that the data carrier has been detected by the remote link
partner. The DCD signal is a MODEM status input and can be read for the appropriate
channel in MSR[7]. This bit reflects the complement of the DCD signal. MSR[3]
indicates if the DCD input has changed state since the previous reading of the
MODEM Status Register. DCD has no effect on the receiver.
Note: Whenever the DCD bit of the MSR changes state, an interrupt is generated if the MODEM Status
Interrupt is enabled.
UART Ring-detector:
When low, RI indicates that a telephone ringing is active. The RI signal is a MODEM
status input and can be read for the appropriate channel in MSR[6]. This bit reflects
the complement of the RI signal. MSR[2] indicates whether the RI input signal has
changed state from low to high since the previous reading of the MSR.
Note: Whenever the RI bit of the MSR changes from a high to a low state, an interrupt is generated if the
MODEM Status Interrupt is enabled.
UART Multi-function Pin:
MF can be programmed for any one of three signal functions OUT2, BAUDOUT or
RXRDY. Bits 2 and 1 of the Alternate Function Register select which output signal will
be present on this pin. OUT2 is the default signal and it is selected immediately after
master reset or power-up.
The OUT2 can be set active low by programming bit 3 (OUT2) of the MCR to a logic
1. A Master Reset operation sets this signal to its inactive (high) state. Loop Mode
holds this signal in its inactive state.
The BAUDOUT signal is the 16X clock output that drives the transmitter and receiver
logic of the associated serial channel. This signal is the result of the XIN clock divided
by the value in the Divisor Latch Registers. The BAUDOUT signal for each channel is
internally connected to provide the receiver clock (formerly RCLK on the PC16550D).
The RXRDY signal can be used to request a DMA transfer of data from the RCVR
FIFO. Details regarding the active and inactive states of this signal are described in
Section 6.5 FIFO CONTROL REGISTER (FCR) and Section 7.9 DMA OPERATION.
7
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