NS16C2552 Datasheet, PDF (5/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

5.0 Pin Descriptions
The NS16C2552/NS16C2752 pins are classified into the
following interface categories.
• Bus Interface
• Serial I/O Interface
• Clock and Reset
• Power supply and Ground pins
Serial channel number (1 or 2) is designated by a numerical
suffix after each pin name. If a numerical suffix (1 or 2) is not
associated with the pin name, the information applies to both
channels.
5.1 PARALLEL BUS INTERFACE
The I/O types are as follows:
Type: I
Type: O
Type: IO_Z
Input
Output
TRI-STATE I/O
Signal
Name
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
Type
IO_Z
I
CS
I
CHSL
I
RD
I
WR
I
RXRDY1
O
RXRDY2
PLCC
Pin #
9
8
7
6
5
4
3
2
15
14
10
18
16
24
20
N/A
TQFP
Pin #
3
2
1
48
47
46
45
44
10
9
4
13
11
20
15
31
8
Description
Data Bus:
Data bus comprises eight TRI-STATE input/output lines. The bus provides
bidirectional communications between the UART and the CPU. Data, control words,
and status information are transferred via the D₇-D₀ Data Bus.
Register Addresses:
Address signals connected to these 3 inputs select a DUART register for the CPU to
read from or write to during data transfer. Table 1 shows the registers and their
addresses. Note that the state of the Divisor Latch Access Bit (DLAB), which is the
most significant bit of the Line Control Register, affects the selection of certain
DUART registers. The DLAB must be set high by the system software to access the
Baud Generator Divisor Latches and the Alternate Function Register.
Chip Select:
When CS is low, the chip is selected. This enables communication between the
DUART and the CPU. Valid chip select should stabilize according to the t_AW
parameter.
Channel Select:
CHSL directs the address and data information to the selected serial channel. (Table
1)
1 = channel 1 is selected.
0 = channel 2 is selected.
IO Read:
The register data is placed on the D0 - D7 on the falling edge of RD. The CPU can
read status information or data from the selected DUART register on the rising edge.
IO Write:
On the falling edge of WR, data is placed on the D0 - D7. On the rising edge, the data
is latched into the selected DUART register.
UART Receive-ready: The receiver DMA signaling is available through this pin which
is a seperate pin on the TQFP package, while on the PLCC package it is available
through the MF pins (19, 35). When operating in the FIFO mode, the CPU selects
one of two types of DMA transfer via FCR[3]. When operating in the 16450 Mode,
only DMA mode 0 is available. Mode 0 supports single transfer DMA (and a transfer is
usually made between CPU bus cycles). Mode 1 supports multi-transfer DMA where
multiple transfers are made continuously until the Rx FIFO is empty. Details regarding
the active and inactive states of this signal are described in Section 6.5 FIFO
CONTROL REGISTER (FCR) and Section 7.9 DMA OPERATION.
5
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