NS16C2552 Datasheet, PDF (32/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

7.0 Operation and Configuration
(Continued)
7.7 SLEEP MODE
To reduce power consumption, NS16C2552/2752 has a per
channel sleep mode when channel is not being used. The
sleep mode requires following conditions to be met:
• Sleep mode of the respective channel is enabled
(IER[4]=1).
• No pending interrupt for the respective channel
(IIR[0]=1).
• Divisor is a non-zero value (DLL or DLM != 0x00).
• Modem inputs are not toggling (MSR[3:0]=0).
• Receiver input is idling at logic 1.
The channel wakes up from sleep mode and returns to
normal operation when one of the following conditions is
met:
• Start bit falling edge (logic 1 to 0) is detected on receiver.
• A character is loaded into the THR or Tx FIFO
• A state change on any of the modem interface inputs,
DTS, DSR, DCD, and RI.
Following the awakening, the channel can fall back into the
sleep mode when all interrupt conditions are serviced and
cleared. If channel is awakened by the modem line inputs,
reading the MSR resets the line inputs.
Following the awakening, the interrupts from the respective
channel has to be serviced and cleared before re-entering
into the sleep mode. The NS16C2552/2752 sleep mode can
be disabled by IER[4]=0.
7.8 INTERNAL LOOPBACK MODE
NS16C2552 incorporates internal loopback path for design
validation and diagnostic trouble shooting. In the loopback
mode, the transmitted data is looped from the transmit shift
register output to the receive shift register input internally.
The system receives its transmitted data. The loopback
mode is enabled by MCR[4]=1 (Figure 13).
In the loopback mode, Tx pin is held at logic 1 or mark
condition while RTS and DTR are de-asserted and CTS,
DRS, CD, and RI inputs are ignored. Note that Rx input must
be held at logic 1 during the loopback test. This is to prevent
false start bit detection upon exiting the loopback mode. RTS
and CTS are disabled during the test.
7.9 DMA OPERATION
LSR[6:5] provide status of the transmit FIFO and LSR[0]
provides the receive FIFO status. User may read the LSR
status bits to initiate and stop data transfers.
More efficient direct memory access (DMA) transfers can be
setup using the RXRDY and TXRDY signals. The DMA
transfers are asserted between the CPU cycles and saves
CPU processing bandwidth. In mode 0, (FCR[3]=0), each
assertion of RXRDY and TXRDY will cause a single transfer.
Note that the user should verify the interface to make sure
the signaling is compatible with the DMA controller.
With built-in transmit and receive FIFO buffers it allows data
to be transferred in blocks (mode 1) and it is ideal for more
efficient DMA operation that further saves the CPU process-
ing bandwidth.
To enable the DMA mode 1, FCR[3]=1. The DMA Rx FIFO
reading is controlled by RXRDY. When FIFO data is filled to
the trigger level, RXRDY asserts and the DMA burst transfer
begins removing characters from Rx FIFO. The DMA trans-
fer stops when Rx FIFO is empty and RXRDY deasserts.
The DMA transmit operation is controlled by TXRDY and is
different between the NS16C2552 and NS16C2752. On the
NS16C2552, the DMA operation is initiated when transmit
FIFO becomes empty and TXRDY is asserted. The DMA
controller fills the Tx FIFO and the filling stops when FIFO is
full and TXRDY is deasserted.
On the NS16C2752, the DMA transfer starts when the Tx
FIFO empty space exceeds the threshold set in FCR[5:4]
and TXRDY asserts. The transfer stops when Tx FIFO is full
and TXRDY desserts. The threshold setting gives CPU more
time to arbitrate and relinquish bus control to DMA controller
providing higher bus efficiency.
7.10 INFRARED MODE
NS16C2552/2752 also integrates an IrDA version 1.0 com-
patible infrared encoder and decoder. The infrared mode is
enabled by MCR[6]=1.
In the infrared mode, the SOUT idles at logic 0. During data
transmission, the encoder transmits a 3/16 bit wide pulse for
each logic 0. With shortened transmitter-on light pulse,
power saving is achieved.
On the receiving end, each light pulse detected translates to
a logic 0, active low (Figure 12.)
20204814
FIGURE 12. IrDA Data Transmission
www.national.com
32