NS16C2552 Datasheet, PDF (28/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

7.0 Operation and Configuration
(Continued)
Character delay time is calculated by using the BAUDOUT
signal as a clock signal. This makes the delay proportional to
the baud rate.
Time-out interrupt is cleared and the timer is reset when the
CPU reads one character from the Receive FIFO. When the
time-out interrupt is inactive the time-out timer is reset after a
new character is received or after the CPU reads the Re-
ceive FIFO.
After the first character is read by the host, the next charac-
ter is loaded into the RBR and the error flags are loaded into
LSR[4:2].
DMA Mode
In the FIFO mode, the RXRDY asserts when the character in
the Rx FIFO reaches the trigger threshold or timeout occurs.
The RXRDY initiates DMA transfer in a burst mode. The
RXRDY deasserts when the Rx FIFO is completely emptied
and the DMA transfer stops (Figure 5.)
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FIGURE 4. Rx FIFO Mode
The RSR operation is described as follows:
1. At the falling edge of the start bit, an internal timer starts
counting at 16X clock. At 8th 16X clock, approximately
the middle of the start bit, the logic level is sampled. If a
logic 0 is detected the start bit is validated.
2. The validation logic continues to detect the remaining
data bits and stop bit to ensure the correct framing. If an
error is detected, it is reported in LSR[4:2].
3. The data frame is then loaded into the RBR and the
Receive FIFO pointer is incremented. The error tags are
updated to reflect the status of the character data in
RBR. The data ready bit (LSR[0]) is set as soon as a
character is transferred from the shift register to the
Receive FIFO. It is reset when the Receive FIFO is
empty.
7.3.1 Receive in FIFO Mode
Interrupt Mode
In the FIFO mode, FCR[0]=1, RBR can be configured to
generate an interrupt after the FIFO pointer reaches a trigger
threshold. The interrupt causes CPU host to fetch the Rx
character in the FIFO in a burst mode and the transfer
number is set by the trigger level. The interrupt is cleared as
soon as the number of bytes in the Rx FIFO drops below the
trigger level. The Rx FIFO continues to receive new charac-
ters, and the interrupt is re-asserted when the character
reaches the trigger threshold.
To ensure the data is delivered to the host, a receive data
ready time-out interrupt IIR[3] is generated when RBR data
is not fetched by the host in 4-word length long (defined in
LCR[1:0]) plus 12 bit-time. The RBR interrupt is enabled
through IER[0]. This is equivalent of 3.6 to 4.7 frame-time.
The maximum time between a received character and a
time-out interrupt will be 147 ms at 300 baud with an 8-bit
receive word.
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FIGURE 5. RXRDY in DMA Mode 1
7.3.2 Receive in non-FIFO Mode
Interrupt Mode
In the non-FIFO mode, FCR[0]=0, RBR can be configured to
generate an IIR Receive Data Available interrupt IIR[2] im-
mediately after the first byte is received. Upon interrupt, the
CPU host reads the RBR and clears the interrupt. The
interrupt is reasserted when the next character is received.
(Figure 6.)
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