NS16C2552 Datasheet, PDF (18/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
6.7 MODEM CONTROL REGISTER (MCR)
This register controls the interface with the MODEM or data
set (or a peripheral device emulating a MODEM). There is a
clock divider for each channel. Each is capable of taking a
common clock input from DC to 80 MHz and dividing the
clock frequency by 1 (default) or 4 depending on the MCR[7]
value. The clock divider and the internal clock division flow is
shown in Figure 1.
20204803
FIGURE 1. Internal Clock Dividers
TABLE 11. MCR (0x4)
R/W
Bit
Bit Name
Def
Description
7
Clk Divider R/W Clock Divider Select
Sel
0
This bit selects the clock divider from crystal or oscillator input. The divider output
connects to the Baud Rate Generator.
1 = Divide XIN frequency by 4.
0 = Divide XIN frequency by 1 (default).
6
IR Mode
R/W Infrared Encoder/Decoder Select
Sel
0
This bit selects standard modem or IrDA interface.
1 = Infrared IrDA Tx/Rx. The data input and output levels complies to the IrDA infrared
interface. The Tx output is at logic 0 during the idle state.
0 = Standard modem Tx/Rx (default).
5
Xon-Any
R/W Xon-Any Enable
Ena
0
This bit enables Xon-Any feature.
1 = Enable Xon-Any function. When Xon/Xoff flow control is enabled, the transmission
resumes when any character is received. The received character is loaded into the Rx
FIFO except for Xon or Xoff characters.
0 = Disable Xon-Any function (default).
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