NS16C2552 Datasheet, PDF (11/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
Reg
Addr RD/
A2-A0 WR
DLL R/W
0x0
Default
DLM R/W
0x1
Default
AFR R/W
0x2
Default
DREV R
0x0
TABLE 2. NS16C2552 Register Summary (Continued)
BIT 7 BIT 6 BIT 5
DLL
Bit 7
X
DLM
Bit 7
X
Rsrvd
DLL
Bit 6
X
DLM
Bit 6
X
Rsrvd
DLL
Bit 5
X
DLM
Bit 5
X
Rsrvd
Bit 7
0
ID
Bit 7
Bit 6
0
ID
Bit 6
Bit 5
0
ID
Bit 5
BIT 4 BIT 3 BIT 2
BIT 1
Baud Rate Generator Divisor
DLL
DLL DLL
DLL
Bit 4
Bit 3 Bit 2
Bit 1
X
X
X
X
DLM DLM DLM
DLM
Bit 4
Bit 3 Bit 2
Bit 1
X
X
X
X
Rsrvd Rsrvd RXRDY BAUDOUT
Bit 4
0
ID
Bit 4
Bit 3
0
DREV
Bit 3
Sel
0
DREV
Bit 2
Sel
0
DREV
Bit 1
BIT 0
DLL
Bit 0
X
DLM
Bit 0
X
Con-
current
WR
0
DREV
Bit 0
Enhanced Registers
EFR R/W Auto Auto Special IER[7:4] SW
SW SW Flow
SW
0x2
CTS RTS Char IIR[5:4] Flow Flow Control Bit 1 Flow
Ena Ena Sel FCR[5:4] Control Control
Control
MCR[7:5] Bit 3 Bit 2
Bit 0
Default
0
0
0
0
0
0
0
0
XON1 R/W XON1 XON1 XON1 XON1 XON1 XON1 XON1
XON1
0x4
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Default
0
0
0
0
0
0
0
0
XON2 R/W XON2 XON2 XON2 XON2 XON2 XON2 XON2
XON2
0x5
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Default
0
0
0
0
0
0
0
0
XOFF1 R/W XOFF1 XOFF1 XOFF1 XOFF1 XOFF1 XOFF1 XOFF1 XOFF1
0x6
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Default
0
0
0
0
0
0
0
0
XOFF2 R/W XOFF2 XOFF2 XOFF2 XOFF2 XOFF2 XOFF2 XOFF2 XOFF2
0x7
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Default
0
0
0
0
0
0
0
0
Comment
LCR[7] = 1
LCR ! 0xBF
LCR[7] = 1
LCR != 0xBF
DLL = 0x00
DLM = 0x00
LCR = 0xBF
Legend
Bit
Name
Default
Value
The Nomenclature of register descriptions:
• Register name, address, register bit, and value example:
FCR 0x2.7:6 = 2’b11 - bits 6 and 7 of FCR are both 1.
Alternative description: FCR[7:6] = 2’b11.
• ‘b - binary number.
• ‘h - hex number.
• 0xNN - hex number.
• n’bN - n is the number of bits; N is the bit value. Example
8’b01010111 = 8’h57 = 0x57.
6.1 RECEIVE BUFFER REGISTER (RBR)
The receiver section contains an 8-bit Receive Shift Register
(RSR) and a 16 (or 64)-byte FIFO that can be accessed
through Receive Buffer Register (RBR).
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