NS16C2552 Datasheet, PDF (14/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
Interrupt
Generation
Rx Trigger
RXRDY
Timer
TXRDY
MSR
Xoff or
Special
character
CTS
RTS
TABLE 8. Interrupt Sources and Clearing (Continued)
Interrupt Sources
Interrupt Clearing
Rx FIFO reached trigger level.
Time-out in 4-word time plus 12-bit delay time.
Read FIFO data until FIFO pointer falls below the
trigger level.
Read RBR.
THR empty.
Any state change in MSR[3:0].
Detection of Xoff or Special character.
Input pin toggles from logic 0 to 1 during CTS
auto flow control mode.
Output pin toggles from logic 0 to 1 during RTS
auto flow control mode.
Read from IIR register or a write to THR.
Read from MSR register.
Read from IIR register or reception of Xon character
(or reception of next character if interrupt is caused by
Special character).
Read from IIR or MSR.
Read from IIR or MSR.
6.5 FIFO CONTROL REGISTER (FCR)
This is a write only register at the same location as the IIR
(the IIR is a read only register). This register is used to
enable the FIFOs, clear the FIFOs, set the FIFO trigger level,
and select the DMA mode.
Mode 0: Mode 0 allows for single transfer in each DMA
cycle. When in the 16450 Mode (FCR[0] = 0) or in the FIFO
Mode (FCR[0] = 1, FCR[3] = 0) and there is at least one
character in the RCVR FIFO or RCVR Buffer Register, the
RXRDY pin will go active low. After going active, the RXRDY
pin will be inactive when there is no character in the FIFO or
Buffer Register.
On The Tx side, TXRDY is active low when XMIT FIFO or
XMIT Holding Register is empty. TXRDY returns to high
when XMIT FIFO or XMIT holding register is not empty.
Mode 1: Mode 1 allows for multiple transfer or multi-
character burst transfer. In the FIFO Mode (FCR[0] = 1,
FCR[3] = 1) when the number of characters in the RCVR
FIFO equals the trigger threshold level or timeout occurs, the
RXRDY goes active low to initiate DMA transfer request. The
RXRDY returns high when RCVR FIFO becomes empty.
In the FIFO Mode (FCR[0] = 1, FCR[3] = 1) when there is (1)
no character in the XMIT FIFO for NS16C2552, or (2) empty
spaces exceed the threshold level for NS16C2752; the
TXRDY pin will go active low. This pin will become inactive
when the XMIT FIFO is completely full.
TABLE 9. FCR (0x2)
Bit
R/W
Bit
Name
Def
Description
7:6
Rx FIFO
W
Rx FIFO Trigger Select
Trig
00
FCR[6] and FCR[7] are used to designate the interrupt trigger level. When the number of
Select
characters in the RCVR FIFO equals the designated interrupt trigger level, a Received Data
Available Interrupt is activated. This interrupt must be enabled by IER[0]=1.
For NS16C2552 with 16-byte FIFO:
FCR[7] FCR[6]
Rx FIFO Trigger Level
1
1
= 14
1
0
=8
0
1
=4
0
0
= 1 (Default)
For NS16C2752 with 64-byte FIFO:
FCR[7] FCR[6]
Rx FIFO Trigger Level
1
1
= 60
1
0
= 56
0
1
= 16
0
0
= 8 (Default)
Refer to Section 7.5 SOFTWARE XON/XOFF FLOW CONTROL and Section 7.9 DMA
OPERATION for software flow control using FIFO trigger level.
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