NS16C2552 Datasheet, PDF (21/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
TABLE 12. LSR (0x5) (Continued)
R/W
Bit
Bit Name
Def
Description
3
Rx Frame
R
Framing Error Indicator
Error
0
This bit is the Framing Error (FE) indicator.
1= Received character did not have a valid Stop bit when the serial channel detects a
logic 0 during the first Stop bit time.
0 = No frame error (default).
The bit is reset to 0 whenever the CPU reads the contents of the Line Status Register
or when the next valid character is loaded into the Receiver Buffer Register. In the
FIFO Mode this error is associated with the particular character in the FIFO it applies
to. This error is revealed to the CPU when its associated character is at the top of the
FIFO. The serial channel will try to resynchronize after a framing error. This assumes
that the framing error was due to the next start bit, so it samples this start bit twice
and then takes in the data.
2
Rx Parity
R
Parity Error Indicator
Error
0
This bit is the Parity Error (PE) indicator.
1 = Received data word does not have the correct even or odd parity, as selected by
the even-parity-select bit during the character Stop bit time when the character has a
parity error.
0 = No parity error (default).
This bit is reset to a logic 0 whenever the CPU reads the contents of the Line Status
Register or when the next valid character is loaded into the Receiver Buffer Register.
In the FIFO mode this error is associated with the particular character in the FIFO it
applies to. This error is revealed to the host when its associated character is at the
top of the FIFO.
1
Rx Overrun
R
Overrun Error Indicator
Error
0
This bit is the Overrun Error (OE) indicator.
This bit indicates that the next character received was transferred into the Receiver
Buffer Register before the CPU could read the previously received character. This
transfer overwrites the previous character. It is reset whenever the CPU reads the
contents of the Line Status Register. If the FIFO mode data continues to fill the FIFO
beyond the trigger level, an overrun error will occur only after the FIFO is full and the
next character has been completely received in the shift register. OE is indicated to
the CPU as soon as it happens. The character in the shift register can be overwritten,
but it is not transferred to the FIFO.
1 = Set to a logic 1 during the character stop bit time when the overrun condition
exists.
0 = No overrun error (default).
0
Rx Data
R
Receiver Data Indicator
Ready
0
This bit is the receiver Data Ready (DR) indicator.
1 = Whenever a complete incoming character has been received and transferred into
the Receiver Buffer Register (RBR) or the FIFO. Bit 0 is reset by reading all of the
data in the RBR or the FIFO.
0 = No receive data available (default).
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