NS16C2552 Datasheet, PDF (10/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
TABLE 2. NS16C2552 Register Summary
Reg
Addr RD/
A2-A0 WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
BIT 1
BIT 0
UART 16C550 Compatible Registers (Default Values Upon Reset)
RBR R/W Data7 Data6 Data5 Data4 Data3 Data2
Data1
Data0
THR
0x0
Default
X
X
X
X
X
X
X
X
IER R/W CTS Int RTS Xoff Int Sleep Md Modem RX Tx Empty
Rx
0x1
Ena
Int
Ena
Ena Stat Int Line
Int Ena Data Int
Ena
Ena Stat
Ena
Int
Ena
Default
0
0
0
0
0
0
0
0
IIR
R FIFOs FIFOs INT INT Src INT INT
INT Src INT Src
0x2
Ena Ena Src
Bit 4
Src
Src
Bit 1
Bit 0
Bit 5
Bit 3 Bit 2
Default
0
0
0
0
0
0
0
1
FCR
W
RX
RX
Tx Tx FIFO DMA Tx
Rx FIFO FIFOs
0x2
FIFO FIFO FIFO Trigger Md FIFO
Reset
Ena
Trigger Trigger Trigger (2752) Ena Reset
(2752)
Default
0
0
0
0
0
0
0
0
LCR R/W Divisor Set Tx Set
Even Parity Stop
Word
Word
0x3
Ena Break Parity Parity Ena Bits
Length Length
Bit 1
Bit 0
Default
0
0
0
0
0
0
0
0
MCR R/W Clk Div IR Md Xon Internal OUT2 OUT1
RTS
DTR
0x4
Sel
Ena Any Loopbk
Output Output
Ena
Control Control
Default
0
0
0
0
0
0
0
0
LSR
R
Rx THR & THR E Rx
Rx
Rx Rx Overrun Rx
0x5
FIFO TSR mpty Break Frame Parity
Error
Data
Gbl Err Empty
Error Error
Ready
Default
0
1
1
0
0
0
0
0
MSR
R
DCD
RI
DSR
CTS Delta Delta
Delta
Delta
0x6
Input Input Input Input DCD RI
DSR
CTS
Default
DCD
RI
DSR
CTS
0
0
0
0
SCR R/W SCR SCR SCR SCR SCR SCR
SCR
SCR
0x7
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Default
1
1
1
1
1
1
1
1
Comment
LCR[7] = 0
LCR != 0xBF
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