NS16C2552 Datasheet, PDF (15/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
TABLE 9. FCR (0x2) (Continued)
Bit
R/W
Bit
Name
Def
Description
5:4
Tx FIFO
W
Transmit FIFO Trigger Level Selection
Trig
00
The transmit FIFO trigger threshold selection is only available in NS16C2752. When
Level Sel
enabled, a transmit interrupt is generated and TXRDY is asserted when the number of empty
spaces in the FIFO exceeds the threshold level.
For NS16C2752 with 64-byte FIFO:
FCR[5] FCR[4] Tx FIFO Trigger Level
1
1
= 56
1
0
= 32
0
1
= 16
0
0
= 8 (Default)
Refer to Section 7.4 TRANSMIT OPERATION and Section 7.9 DMA OPERATION for
transmit FIFO descriptions.
These two bits are reserved in NS16C2552 and have no impact when they are written to.
3
DMA
W
DMA Mode Select
Mode
Select
0
This bit controls the RXRDY and TXRDY initiated DMA transfer mode.
1 = DMA Mode 1. Allows block transfers. Requires FCR 0x2.0=1 (FIFO mode).
0 = DMA Mode 0 (default). Single transfers.
2
Tx FIFO
W
Transmit FIFO Reset
Reset
0
This bit is only active when FCR bit 0 = 1.
1 = Reset XMIT FIFO pointers and all bytes in the XMIT FIFO (the Tx shift register is not
cleared and is cleared by MR reset). This bit has the self-clearing capability.
0 = No impact (default).
Note: Reset pointer will cause the characters in Tx FIFO to be lost.
1
Rx FIFO
W
Receive FIFO Reset
Reset
0
This bit is only active when FCR bit 0 = 1.
1 = Reset RCVR FIFO pointers and all bytes in the RCVR FIFO (the Rx shift register is not
cleared and is cleared by MR reset). This bit has the self-clearing capability.
0 = No impact (default).
Note: Reset pointer will cause the characters in Rx FIFO to be lost.
0
Tx and
W
Transmit and Receive FIFO Enable
Rx FIFO
Enable
0
1 = Enable transmit and receive FIFO. This bit must be set before other FCR bits are
written. Otherwise, the FCR bits can not be programmed.
0 = Disable transmit and receive FIFO (default).
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