NS16C2552 Datasheet, PDF (29/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

7.0 Operation and Configuration
(Continued)
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FIGURE 6. Rx Non-FIFO Mode
DMA Mode
In the non-FIFO mode, the presence of a received character
in RBR causes the assertion of RXRDY at which point DMA
transfer can be initiated. Upon transfer completion RXRDY is
deasserted. DMA transfer stops and awaits for the next
character. (Figure 7.)
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FIGURE 7. RXRDY in DMA Mode 0
7.3.3 Receive Hardware Flow Control
On the line side, RTS signal provides automatic flow control
to prevent data overflow in the Receive FIFO. The RTS is
used to request remote unit to suspend or resume data
transmission. This feature is enabled to suit specific applica-
tion. The RTS flow control can be enabled by the following
steps:
• Enable auto-RTS flow control EFR[6]=1.
• The auto-RTS function is initiated by asserting RTS out-
put pin, MCR[1]=1.
The auto-RTS assertion and deassertion timing is based
upon the Rx FIFO trigger level (Table 27 and Table 28).
7.3.4 Receive Flow Control Interrupt
To enable auto RTS interrupt:
• Enable auto RTS flow control EFR[6]=1.
• Enable RTS interrupt IER[6]=1.
An interrupt is generated when RTS pin makes a transition
from logic 0 to 1; IIR[5] is set to logic 1.
The receive data ready interrupt (IIR[2]) generation timing is
based upon the Rx FIFO trigger level (Table 27 and Table
28).
TABLE 27. Auto-RTS HW Flow Control on NS16C2552
Rx Trigger
Level
1
4
8
14
INTR Pin
Activation
1
4
8
14
RTS
Desertion
2
8
14
14
RTS
Assertion
0
1
4
8
TABLE 28. Auto-RTS HW flow Control on NS16C2752
Rx Trigger
Level
8
16
56
60
INTR Pin
Activation
8
16
56
60
RTS
Desertion
16
56
60
60
RTS
Assertion
0
8
16
56
7.4 TRANSMIT OPERATION
Each serial channel consists of an 8-bit Transmit Shift Reg-
ister (TSR) and a 16-byte (or 64-byte) Transmit FIFO. The
Transmit FIFO includes a 8-bit Transmit Holding Register
(THR). The TSR shifts data out at the 16X internal clock. A
bit time is 16 clock periods. The transmitter begins with a
start-bit followed by data bits, asserts parity-bit if enabled,
and adds the stop-bit(s). The FIFO and TSR status is re-
ported in the LSR[6:5].
The THR is an 8-bit register providing a data interface to the
host processor. The host writes transmit data to the THR.
The THR is the Transmit FIFO input register in FIFO opera-
tion. The FIFO operation can be enabled by FCR[0]=1.
During the FIFO operation, the FIFO pointer is incremented
pointing to the next FIFO location when a data word is
written into the THR.
7.4.1 Transmit in FIFO Mode
Interrupt mode
In the NS16C2752 FIFO mode (FCR[0]=1), when the Tx
FIFO empty spaces exceed the threshold level the THR
empty flag is set (LSR[5]=1). The THR empty flag generates
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