NS16C2552 Datasheet, PDF (24/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
6.12 ALTERNATE FUNCTION REGISTER (AFR)
This is a read/write register used to select simultaneous
write to both register sets and alter MF pin functions.
Bit Name
Bit
Default
7:3
Reserved
2:1
MF Output Sel
TABLE 18. AFR (0x2, LCR[7] = 1, LCR != 0xBF)
R/W
Def
Description
Reserved
These bits are set to a logic 0.
R/W
Multi-function Pin Output Select
0
These select the output signal that will be present on the multi-function pin, MF.
These bits are individually programmable for each channel, so that different signals
can be selected on each channel.
AFR[2] AFR[1]
MF Function
1
1
= Reserved (MF output is forced logic 1)
1
0
= RXRDY
0
1
= BAUDOUT
0
0
= OUT2 (default)
0
Concurrent
R/W
Concurrent Write Enable
Write Ena
0
1 = CPU can write concurrently to the same register in both registers sets. This
function is intended to reduce the DUART initialization time. It can be used by a CPU
when both channels are initialized to the same state. The CPU can set or clear this bit
by accessing either register set. When this bit is set the channel select pin still selects
the channel to be accessed during read operations. Setting or clearing this bit has no
effect on read operations.
The user should ensure that the DLAB bit LCR[7] of both channels are in the same
state before executing a concurrent write to register addresses 0, 1 and 2.
0 = No concurrent write (default). (No impact on read operations.)
6.13 DEVICE IDENTIFICATION REGISTER (ID)
The device ID for NS16C2552 is 0x03. DLL and DLM should
be initialized to 0x00 before reading the ID register. This is a
read-only register.
TABLE 19. DREV (0x0, LCR[7]=1, LCR!=0xBF, DLL=DLM=0x00)
R/W
Bit
Bit Name
Def
Description
7:4
Device ID
R
Device ID
Value = 0x3 for NS16C2552; 0x2 for NS16C2752
3:0
Device Rev
R
Device Revision
Value = 0x1.
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