NS16C2552 Datasheet, PDF (38/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

10.0 DC and AC Specifications (Continued)
Symbol
t_HZ
t_WR
t_DY
t_DS
t_DH
t_MDO
t_SIM
t_RIM
t_SINT
t_RINT
t_STI
t_WST
t_HR
t_WXI
t_SXA
t_SSR
t_RXI
Parameter
Data Disable Time
WR Strobe Width
Write Cycle Delay
Data Setup Time
Data Hold Time
Delay from WR to Output
Delay from Modem input to
Interrupt output
Delay to Reset interrupt from
RD falling edge
Delay from Stop to Interrupt
Set
Delay from of RD to Reset
Interrupt
Delay from center of Start to
INTR Set
Delay from WR to Transmit
Start
Delay from WR to interrupt
clear
Delay from WR to TXRDY
rising edge
Delay from Center of Start to
TXRDY falling edge
Delay from Stop to RXRDY
falling edge
Delay from /RD to RXRDY
rising edge
Condition
3.3V Limits
Min
Max
0
18
35
35
12
4
Modem Control
20
20
23
Line Receive and Transmit
(Note 2)
4
45
16
0
16
34
DMA Interface
27
8
4
27
5.0V Limits
Min
Max
0
18
24
24
12
4
15
15
17
Units
ns
ns
ns
ns
ns
ns
ns
ns
4
Bclk
30
ns
10
ns
0
16
Bclk
22
ns
18
ns
8
Bclk
4
Bclk
18
ns
Note 1: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited
to those conditions specified under DC electrical characteristics.
Note 2: The B_CLK period decreases with increasing reference clock input. At higher clock input frequency, the number of B_CLK increases.
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