NS16C2552 Datasheet, PDF (22/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
6.9 MODEM STATUS REGISTER (MSR)
This register provides the current state of the control lines
from the MODEM (or peripheral device) to the CPU. In
addition to this current-state information, four bits of the
MODEM Status Register provide change information. The
latter bits are set to a logic 1 whenever a control input from
the MODEM changes state. They are reset to logic 0 when-
ever the CPU reads the MODEM Status Register.
TABLE 13. MSR (0x6)
R/W
Bit
Bit Name
Def
Description
7
DCD Input
R
DCD Input Status
Status
DCD This bit is the complement of the Data Carrier Detect (DCD) input. In the loopback mode,
this bit is equivalent to the OUT2 of the MCR.
1 = DCD input is logic 0.
0 = DCD input is logic 1.
6
RI Input
R
RI Input Status
Status
RI
This bit is the complement of the Ring Indicator (RI) input. In the loopback mode, this bit is
equivalent to OUT1 of the MCR.
1 = RI input is logic 0.
0 = RI input is logic 1.
5
DSR Input
R
DSR Input Status
Status
DSR This bit is the complement of the Data Set Ready (DSR) input. In the loopback mode, this
bit is equivalent to DTR in the MCR.
1 = DSR input is logic 0.
0 = DSR input is logic 1.
4
CTS Input
R
CTS Input Status
Status
CTS This bit is the complement of the Clear to Send (CTS) input. In the loopback mode, this bit
is equivalent to RTS in the MCR.
1 = CTS input is logic 0.
0 = CTS input is logic 1.
3
DDCD
R
Delta DCD Input Indicator
Input
Status
0
This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the DCD
input has changed state since the last read by the host.
1 = DCD input has changed state.
0 = DCD input has no state change (default).
Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEM Status Interrupt is generated.
2
Falling
R
Falling Edge RI Indicator
Edge RI
Indicator
0
This bit is theFalling Edge of Ring Indicator (TERI) detector. Bit 2 indicates that the RI
input pin has changed from a logic 0 to 1 since the last read by the host.
1 = RI input has changed state from logic 0 to 1.
0 = RI input has no state change from 0 to 1 (default).
1
DDSR
R
Delta DSR Input Indicator
Input
Indicator
0
This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the DSR input
pin has changed state since the last read by the host.
1 = DSR input has changed state from logic 0 to 1.
0 = DSR input has no state change from 0 to 1 (default).
0
DCTS
R
Delta CTS Input Indicator
Input
Indicator
0
This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input pin
has changed state since the last time it was read by the host.
1 = CTS input has changed state.
0 = CTS input has no state change (default).
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