NS16C2552 Datasheet, PDF (27/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

7.0 Operation and Configuration
7.1 CLOCK INPUT
The NS16C2552/2752 has an on-chip oscillator that accepts
standard crystal with parallel resonant and fundamental fre-
quency. The generated clock is supplied to both UART chan-
nels with the capability range from DC to 24 MHz. The
frequency of the clock oscillator is divided by 16 internally,
combined with an on-chip programmable clock divider pro-
viding the baud rate for data transmission. The divisor is
16-bit with MSB byte in DLM and LSB byte in DLL. The
divisor calculation is shown in Section 6.11 PROGRAM-
MABLE BAUD GENERATOR.
The external oscillator circuitry requires two load capacitors,
a parallel resistor, and an optional damping resistor. The
oscillator circuitry is shown in Figure 2.
20204804
FIGURE 2. Crystal Oscillator Circuitry
The requirement of the crystal is listed in Table 25.
TABLE 25. Crystal Component Requirement
Parameter
Crystal Frequency Range
Crystal Type
C1 & C2, Load Capacitance
ESR
Frequency Stability 0 to 70˚C
Value
<= 24 MHz
Parallel resonant
Fundamental
10 - 22 pF
20 - 120 Ω
100 ppm
The capacitors C1 and C2 are used to adjust the load
capacitance on these pins. The total load capacitance (C1,
C2 and crystal) must be within a certain range for the
NS16C2552/2752 to function properly. The parallel resistor
Rp and load resistor Rs are recommended by some crystal
vendors. Refer to the vendor’s crystal datasheet for details.
Since each channel has a separate programmable clock
divider, each channel can have a different baud rate.
The oscillator provides clock to the internal data transmis-
sion circuitry, writing and reading from the parallel bus is not
affected by the oscillator frequency. For circuits not using the
external crystal, the clock input is XIN (Figure 3.)
20204805
FIGURE 3. Clock Input Circuitry
7.2 RESET
The NS16C2552/2752 has an on-chip power-on reset. An
external active high reset can also be applied. The default
output state of the device is listed in Table 26.
TABLE 26. Output State After Reset
Output
SOUT1, SOUT2
OUT2
RTS1, RTS2
DTR1, DTR2
INTR1, INTR2
TXRDY1, TXRDY2
Reset State
Logic 1
Logic 1
Logic 1
Logic 1
Logic 0
Logic 0
7.3 RECEIVER OPERATION
Each serial channel consists of an 8-bit Receive Shift Reg-
ister (RSR) and a 16 (or 64) -byte by 11-bit wide Receive
FIFO. The RSR contains a 8-bit Receive Buffer Register
(RBR) that is part of the Receive FIFO. The 11-bit wide FIFO
contains an 8-bit data field and a 3-bit error flag field. The
RSR uses 16X clock as timing source. (Figure 4.)
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