NS16C2552 Datasheet, PDF (23/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
6.10 SCRATCHPAD REGISTER (SCR)
This 8-bit Read/Write Register does not control the serial
channel in any way. It is intended as a Scratchpad Register
to be used by the programmer to hold data temporarily.
Bit
Bit Name
7:0
SCR Data
R/W
Def
R/W
0xFF
TABLE 14. SCR (0x7)
Description
Scratchpad Register
This 8-bit register does not control the UART in any way. It is intended as a
scratchpad register to be used by the programmer to hold temporary data.
6.11 PROGRAMMABLE BAUD GENERATOR
The NS16C2552 contains two independently programmable
Baud Generators. Each is capable of taking prescaler input
and dividing it by any divisor from 1 to 2¹⁶ -1 (Figure 1). The
highest input clock frequency recommended with a divisor =
1 is 80MHz. The output frequency of the Baud Generator is
16 X the baud rate, [divisor # = (frequency input) / (baud rate
X 16)]. The output of each Baud Generator drives the trans-
mitter and receiver sections of the associated serial channel.
Two 8-bit latches per channel store the divisor in a 16-bit
binary format. These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud Genera-
tor. Upon loading either of the Divisor Latches, a 16-bit Baud
Counter is loaded.
TABLE 15. DLL (0x0, LCR[7] = 1, LCR != 0xBF)
Bit Bit Name
7:0 DLL Data
R/W
Def
R/W
0xXX
Description
Divisor Latch LSB
This 8-bit register holds the least significant byte of the 16-bit baud rate generator divisor.
Note: This register value does not change upon MR reset.
Bit Bit Name
7:0 DLM Data
R/W
Def
R/W
0xXX
TABLE 16. DLM (0x1, LCR[7] = 1, LCR != 0xBF)
Description
Divisor Latch MSB
This 8-bit register holds the most significant byte of the 16-bit baud rate generator divisor.
Note: This register value does not change upon MR reset.
Table 17 provides decimal divisors to use with crystal fre-
quencies of 1.8432 MHz, 3.072 MHz and 18.432 MHz. For
baud rates of 38400 and below, the error obtained is mini-
mal. The accuracy of the desired baud rate is dependent on
the crystal frequency chosen. Using a divisor of zero is not
recommended.
TABLE 17. Baud Rate Generation Using 1.8432 MHz Clock with MCR[7]=0
Output Data
Baud Rate
50
75
150
300
600
1200
2400
4800
9600
19,200
38,400
115,200
Output 16x Clock
Divider (dec)
2304
1536
768
384
192
96
48
24
12
6
3
1
User 16x Clock
Divisor (hex)
900
600
300
180
C0
60
30
18
0C
06
03
01
DLM Program
Value (hex)
09
06
03
01
00
00
00
00
00
00
00
00
DLL Program
Value (hex)
00
00
00
80
C0
60
30
18
0C
06
03
01
Data Rate
Error (%)
0
0
0
0
0
0
0
0
0
0
0
0
Note: For baud rates of 250k, 300k, 375k, 500k, 750k and 1.5M using a
24MHz crystal causes minimal error.
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