NS16C2552 Datasheet, PDF (25/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
6.14 ENHANCED FEATURE REGISTER (EFR)
This register enables the enhanced features of the device.
TABLE 20. EFR (0x2, LCR = 0xBF)
Bit Name R/W
Bit
Default
Def
Description
7
Auto CTS R/W Automatic CTS Flow Control Enable
Flow Ctl
Ena
0
1 = Enable automatic CTS flow control. Data transmission stops when CTS input deasserts to
logic 1. Data transmission resumes when CTS returns to logic 0.
0 = Automatic CTS flow control is disabled (Default)
6
Auto RTS R/W Automatic RTS Flow Control Enable
Flow Ctl
Ena
0
By setting EFR[6] to logic 1, RTS output can be used for hardware flow control. When Auto
RTS is selected, an interrupt is generated when the receive FIFO is filled to the programmed
trigger level and RTS de-asserts to a logic 1. The RTS output must be logic 0 before the auto
RTS can take effect. RTS pin functions as a general purpose output when hardware flow
control is disabled.
1 = Enable automatic RTS flow control.
0 = Automatic RTS flow control is disabled (Default)
5
Special
R/W Special Character Detect Enable
Char Det
Ena
0
1 = Special character detect enabled. The UART compares each incoming received character
with data in Xoff-2 register (0x4, LCR = 0xBF). If a match is found, the received data will be
transferred to FIFO and IIR[4] is set to indicate the detection of a special character if IER[5] =
1. Bit 0 corresponds with the LSB of the received character. If flow control is set for
comparing Xon1, Xoff1 (EFR[1:0] = 10) then flow control and special character work normally;
If flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special
character interrupt if IER[5] is enabled. Special character interrupts are cleared automatically
after the next received character.
0 = Special character detect disabled. (Default)
4
Enhanced R/W Enhanced Function Bits Enable
Fun Bit
0
This bit enables IER[7:4], FCR[5:4], and MCR [7:5] to be changed. After changing the
Ena
enhanced bits, EFR[4] can be cleared to logic 0 to latch in the updated values. EFR[4] allows
compatibility with the legacy mode software by disabling alteration of the enhanced functions.
1 = Enables writing to IER[7:4], FCR[5:4], and MCR [7:5].
0 = Disable writing to IER[7:4], FCR[5:4], MCR [7:5] and, latching in updated value. Upon
reset, IER[7:4], IIR[5:4], FCR[5:4], and MCR [7:5] are cleared to logic 0. (Default)
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