NS16C2552 Datasheet, PDF (30/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

7.0 Operation and Configuration
(Continued)
a TXRDY interrupt (IIR[1]=1) when the transmit empty inter-
rupt is enabled (IER[1]=1). Writing to THR or reading from
IIR deasserts the interrupt.
There is a two-character hysteresis in interrupt generation.
The host needs to service the interrupt by writing at least two
characters into the Tx FIFO before the next interrupt can be
generated.
The NS16C2552 does not have the FIFO threshold level
control. The interrrupt is generated when the FIFO is com-
pletely empty.
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FIGURE 9. TXRDY in DMA Mode 1
7.4.2 Transmit in non-FIFO Mode
Interrupt Mode
The THR empty flag LSR[5] is set when a data word is
transferred to the TSR. THR flag can generate a transmit
empty interrupt IIR[1] enabled by IER[1]. The TSR flag
LSR[6] is set when TSR becomes empty. The host CPU may
write one character into the THR and wait for the next IIR[1]
interrupt. (Figure 10.)
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FIGURE 8. Tx FIFO Mode
DMA mode
To fully take advantage of the FIFO buffer, the UART is best
operating in DMA mode 1 (FCR[3]=1) when characters are
transferred in bursts. The NS16C2752 has a Tx FIFO thresh-
old level control in register FCR[5:4]. The threshold level
sets the number of empty spaces in the FIFO and deter-
mines when the TXRDY is asserted. If the number of empty
spaces in the FIFO exceeds the threshold, the TXRDY as-
serts initiating DMA transfers to fill the Tx FIFO. When the
empty spaces in the Tx FIFO becomes zero (i.e., FIFO is
full), the TXRDY deasserts and the DMA transfer stops.
TXRDY reasserts when empty space exceeds the set
threshold, starting a new DMA transfer cycle. (Figure 9.)
The NS16C2552 does not have the FIFO threshold level
control. The TXRDY is asserted when FIFO is empty and
deasserted when FIFO is full. It is equivalent of having
trigger threshold set at 16 empty spaces.
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FIGURE 10. Tx Non-FIFO Mode
DMA mode
In the DMA single transfer (mode 0), TXRDY asserts when
FIFO is empty initiating one DMA transfer and deasserts
when a character is written into the FIFO. (Figure 11.)
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