NS16C2552 Datasheet, PDF (13/43 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

6.0 Register Set (Continued)
Bit
Bit Name
0
Rx_DV Int
Ena
TABLE 5. IER (0x1) (Continued)
R/W
Def
Description
R/W Rx Data Available Interrupt Enable
0
1 = Enable the Received Data Available and FIFO mode time-out interrupt.
0 = Disable the Received Data Available interrupt (default).
6.4 INTERRUPT IDENTIFICATION REGISTER (IIR)
In order to provide minimum software overhead during data
word transfers, each serial channel of the DUART prioritizes
interrupts into seven levels and records these levels in the
Interrupt Identification Register. The seven levels of interrupt
conditions are listed in Table 7. When the CPU reads the IIR,
the associated DUART serial channel freezes all interrupts
and indicates the highest priority pending interrupt to the
CPU. While this CPU access is occurring, the associated
DUART serial channel records new interrupts, but does not
change its current indication until the access is complete.
Table 6 shows the contents of the IIR.
TABLE 6. IIR (0x2)
R/W
Bit
Bit Name
Def
Description
7:6
FIFOs Ena
R
FIFO Enable Status (FCR 0x2.0)
00
2’b11 = Tx and Rx FIFOs enabled.
2’b00 = Tx and Rx FIFOs disabled (default).
5
INT Src 5
R
RTS/CTS Interrupt Status
0
1 = RTS or CTS changed state from low to high.
0 = No change on RTS or CTS from low to high (default).
4
INT Src 4
R
Xoff or Special Character Interrupt Status
0
1 = Receiver detected Xoff or special character.
0 = No Xoff character match (default).
3:1
INT Src 3:1
R
Interrupt Source Status
000
These three bits indicates the source of a pending interrupt. Refer to Table 7 for
interrupt source and priority.
0
INT Src 0
R
Interrupt Status
1
1 = No interrupt is pending (default).
0 = An interrupt is pending and the IIR content may be used as a pointer for the
interrupt service routine.
TABLE 7. Interrupt Source and Priority Level
Priority
IIR Register Status Bits
Level
5
4
3
2
1
0
Interrupt Source
1
0
0
0
1
1
0 LSR
2
0
0
1
1
0
0 RXRDY (Receive data time-out)
3
0
0
0
1
0
0 RXRDY (Receive data ready)
4
0
0
0
0
1
0 TXRDY (Transmit data ready)
5
0
0
0
0
0
0 MSR (Modem Status Register)
6
0
1
0
0
0
0 RXRDY (Received Xoff or special character)
7
1
0
0
0
0
0 CTS, RTS change state from low to high
-
0
0
0
0
0
1 None (default)
Interrupt
Generation
LSR
TABLE 8. Interrupt Sources and Clearing
Interrupt Sources
Any bit is set in LSR[4:1] (Break Interrupt,
Framing, Rx parity, or overrun error).
Interrupt Clearing
Read LSR register. (Interrupt flags and tags are not
cleared until the character(s) that generated the
interrupt(s) has/have been emptied or cleared.)
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