NT5DS4M32EG Datasheet, PDF (9/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory location (write cycle), or from memory
location (read cycle). There are two parameters that define how the burst mode operates. These parameters including
burst sequence and burst length are programmable and determined by address A0 ~ A3 during the Mode Register Set
command. The burst type is used to define the sequence in which the burst data will be delivered or stored to the DDR
SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the below table. The burst
length controls the number of bits that will be output after a read command, or the number of bits to be input after a
write command. The burst length can be programmed to have values of 2,4,8 or full page. For the full page operation,
the starting address must be an even number and the burst stop at the end of burst.
Table 3: Burst Length and Sequence
Burst Length
2
4
8
Full Page (256)
Starting Address (A₂, A₁, A₀)
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
n = A0 - A7, A0 = 0
Sequential Mode
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2, ..., Cn-1
Interleave Mode
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-0-1-2-3
7-6-5-4-3-2-1-0
Not supported
Bank Activation Command
The Bank Activation command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of
the clock. The DDR SDRAM has four independent Banks, so two Bank Select Addresses(BA0, BA1) are supported.
The Bank Activation command must be applied before any Read or Write operation is executed.The delay from the
Bank Activation command to the first read or write command must meet or exceed the minimum of /RAS to /CAS delay
time (tRCDR/tRCDW min). Once a bank has been activated, it must be precharged before another Bank Activation
command can be applied to the same bank. The minimum time interval between interleaved Bank Activation
commands(Bank A to B and vice versa) is the Bank to Bank delay time (tRRD min).
Figure 7: Bank Activation Command Cycle (/CAS Latency = 3)
0
1
/CK
CK
Address
Bank A
Row Addr.
2
Bank A
Col. Addr.
/RAS-/CAS delay time (tRCDR for READ)
Command
Bank A
A ct ivate
NOP
NOP
READ A
with Auto
Precharge
Row cycle Time (tRC)
n
n+1
n+2
Bank A
Row Addr.
Bank B
Row Addr.
/RAS-/RAS delay time (tRRD)
Bank A
A ct ivate
NOP
Bank B
A ct ivate
: Don’t care
Doc # 14-02-045 Rev A ECN 01-1118
9
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.