NT5DS4M32EG Datasheet, PDF (11/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
Burst Interruption
Read Interrupted by Read
NT5DS4M32EG
Advance Information
Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the
previous burst is interrupted, the remaining address are overridden by the new address with the full burst length. The
data from the previous Read command continues to appear on the outputs until the /CAS latency from the interrupting
Read command is satisfied. Read to Read interval is minimum 1 tCK.
Figure 10: Burst Interrupted by Read (Burst length = 4, /CAS Latency = 3)
0
1
2
3
4
5
6
7
8
/CK
CK
Command ^{READ A READ B NOP}
NOP
NOP
NOP
NOP
NOP
NOP
/CAS Latency = 3
DQS
DQ’s
Douta0 Douta1 Doutb0 Doutb1 Doutb2 Doutb3
Read Interrupted by Burst stop & Write
To interrupt Burst Read with a write command, Burst stop command must be asserted to avoid data contention on
the I/O bus by placing the DQ’s(Output drivers) in a high impedance state at least one clock cycle before the Write
Command is initiated. Once the burst stop command has been issued, the minimum delay to a write command is
CL(RU). [CL is /CAS Latency and RU means round up to the nearest integer.]
Figure 11: Burst Interrupted by Burst Stop & Write (Burst Length = 4, /CAS Latency = 3)
0
1
2
3
4
5
6
7
8
/CK
CK
Command
READ
Burst
stop
/CAS Latency = 3
DQS
DQ’s
NOP
NOP
NOP
t RPRE
Preamble
Dout0 Dout1
WRITE NOP
t DQSS
t WPREH
NOP
t WPRES
Din 0 Din 1 Din 2 Din 3
Doc # 14-02-045 Rev A ECN 01-1118
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.