NT5DS4M32EG Datasheet, PDF (6/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
FUNCTIONAL DESCRIPTION
Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VREF & VTT
2. Start clock and maintain stable condition for minimum 200µs
3. The minimum of 200µs after stable power and clock (CK,/CK), apply NOP and CKE to be high.
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 Every “DLL Enable” command resets DLL. Therefore sequence 6 can be skipped during power-up.
Instead of it, the additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
Figure 4: Power-Up & Initialization Sequence
/CK
CK
tRP
Command
Precharge
ALL Banks
Input must be
stable for 200us
2C lo ck
2C lo ck
min.
min.
tRP
EMRS
MRS
DLL Reset
Precharge
ALL Banks
tRF C
1st Auto
Refresh
2nd Auto
Refresh
200 Clock min.
tRF C
2C lo ck
min.
Mode
Register Set
Any
Command
Doc # 14-02-045 Rev A ECN 01-1118
6
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.