NT5DS4M32EG Datasheet, PDF (12/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
Read Interrupted by Precharge
NT5DS4M32EG
Advance Information
Burst Read can be interrupted by precharge of the same bank. The minimum 1 clock cycle is required for the read
precharge interval. Precharge command to output disable latency is equivalent to the /CAS latency.
Figure 12: Burst Interrupted by Precharge (Burst Length = 8, /CAS Latency = 3)
/CK
CK
Command
0
1
2
1t CK
READ Precharge
NOP
3
NOP
4
NOP
5
NOP
6
NOP
7
NOP
8
NOP
/CAS Latency = 3
DQS
DQ’s
t RPRE
t RPST
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
Interrupted by precharge
Write Interrupted by Write
Burst Write can be interrupted by the new Write Command before completion of the previous burst write, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When the previous
burst is interrupted, the remaining addresses are overridden by the new addresses and data will be written into the
device until the programmed burst length is satisfied.
Figure 13: Write Interrupted by Write (Burst Length = 4)
/CK
CK
Command
0
1
2
3
4
5
NOP
1t CK
WRITEA WRITEB
NOP
NOP
NOP
/CAS Latency = 3
DQS
DQ’s
t WPREH
t WPRES
Din a0 Din a1 Din b0 Din b1 Din b2 Din b3
6
NOP
7
NOP
8
NOP
Doc # 14-02-045 Rev A ECN 01-1118
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.