NT5DS4M32EG Datasheet, PDF (3/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
Table 2: INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, /CK^#
CKE
/CS
/RAS
/CAS
/WE
DQS₀ ~ DQS₃
DM₀ ~ DM₃
DQ₀ ~ DQ₃₁
BA₀ ~ BA₁
A₀ ~ A₁₁
V_DD, V_SS
V_DDQ, V_SSQ
V_REF
NC/RFU
MCL
Type
Input
Input
Input
Input
Input
Input
Input, Output
Input
Input, Output
Input
Input
Power Supply
Power Supply
Power Supply
No Connection/
Reserved for future
use
Must Connect Low
Function
The differential system clock inputs.
All of the input are sampled on the rising edge of the clock except DQ’s
and DM’s that are sampled on both edges of the DQS.
CKE high activates and CKE low deactivates the internal clock,input buff-
ers and output drivers. By deactivating the clock, CKE low indicates the
Power down mode or Self refresh mode.
/CS enables(registered Low) and disables(registered High) the command
decoder. When /CS is registered High,new commands are ignored but
previous operations are continued.
Latches row addresses on the positive going edge of the CK with /RAS
low. Enables row access & precharge.
Latches Column addresses on the positive going edge of the CK with /
CAS low. Enables column access.
Enables write operation and row precharge. Latches data in starting from /
CAS, /WE active.
Data inputs and outputs are synchronized with both edge of DQS.
DQS0 for DQ0~DQ7, DQS1 for DQ8~DQ15, DQS2 for DQ16~DQ23,
DQS3 for DQ24~DQ31
Data-In mask. Data-In is masked by DM Latency=0 when DM is high in
burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~
DQ23, DM3 for DQ24 ~ DQ31.
Data inputs and outputs are multiplexed on the same pins.
Select which bank is to be active.
Row,Column addresses are multiplexed on the same pin. Row address :
RA0 ~ RA11, Column address : CA0 ~ CA7. Column address CA8 is used
for auto precharge.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved
noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommend to be left “No Connection” on the device.
Not internally connected
# : The timing reference point for the differential clocking is the cross point of CK and /CK.
For any applications using the single ended clocking, apply VREF to /CK pin.
Doc # 14-02-045 Rev A ECN 01-1118
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.