NT5DS4M32EG Datasheet, PDF (8/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
Extended Mode Register Set (EMRS)
NT5DS4M32EG
Advance Information
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The
default value of the extended mode register is not defined, therefore the extended mode register must be written after
power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /
WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended mode register). The state of address pins A0,A2~A5, A7~A11 and BA1 in the same cycle as /CS,/RAS,/CAS
and /WE going low are written in the extended mode register. A1and A6 are used for setting driver strength to weak or
matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The
mode register contents can be changed using the same command and clock cycle requirements during operation as
long as all banks are in the idle state A0 is used for DLL enable or disable.“High”on BA0 is used for EMRS. All the
other address pins except A0,A1, A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for
specific codes.
BA 1
BA 0
A 11
A 10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
RFU
1
RFU
DIC
RFU
DIC
DLL
Extended
Mode Register
BA 0
Mode
0
MRS
1
EMRS
A6
A1
0
1
1
1
Output Driver Impedance Control
Weak
60% of full drive strength
Matched impedance
30% of full drive strength
• RFU(Reserved for Future Use) should stay “0” during MRS cycle.
A0 DLL Enable
0
Enable
1
Disable
Figure 6: LOW Frequency Operation Mode
DLL DISABLE MODE
/CK
CK
2C lo ck
2C lo ck
DLL Disable
tRP
min.
min.
Mode
2C lo ck
2C lo ck
2C lo ck
tRP
min.
min.
min.
Command
Precharge
ALL Banks
EMRS
MRS^{* 1}
CMD
Precharge
ALL Banks
EMRS
MRS
DLL RESET
MRS
Ac tive
Read^*2
Enter DLL
Disable
Mode
C L=2/3
BL=F REE
Exit DLL
Disable
Mode
200 Clock min.
Notes:
- DLL disable mode is operating mode for low operating frequency between 143MHz and 83MHz without DLL.
- This DLL disable mode is useful for power saving.
- All banks precharge or a bank precharge command can omit before entering and exiting DLL disable mode.
*1 : CL=2 & 3 and BL can set any burst length at DLL disable mode.
*2 : A Read command can be applied as far as tRCD is satisfied after any bank active command.
And it needs an additional 200 clock cycles for read operation after exiting DLL disable mode.
Doc # 14-02-045 Rev A ECN 01-1118
8
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.