NT5DS4M32EG Datasheet, PDF (7/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
Mode Register Set (MRS)
NT5DS4M32EG
Advance Information
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs /CAS
latency, address mode, burst length, test mode, DLL reset and various vendor specific option to make DDR SDRAM
useful for variety of different applications. The default value of the mode register is not defined, therefore the mode
register must be written after EMRS setting for proper operation. The mode register is written by asserting low on /CS,
/RAS, /CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode
register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as /CS, /RAS, /CAS and /WE going low
is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode
register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on
functionality. The burst length uses A0~A2, address mode uses A3, /CAS latency (read latency from column address)
uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL for DLL reset. A7, A8, BA0, and BA1 must be set to low for
normal MRS operation. Refer to the table for specific codes for various burst length, address modes and /CAS
latencies.
BA 1
BA 0
A 11
A 10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
RFU
0
RFU
DLL
TM
/CAS Latency
DLL
A8
DLL Reset
0
No
1
Yes
BA 0
Mode
0
MRS
1
EMRS
* RFU(Reserved for future use)
should stay “0” during MRS cycle.
Test Mode
A7
Mode
0
Normal
1
Test
/CAS Latency
A6
A5
A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
BT
Burst Length
Burst Type
A3
Type
0
Seque nt ial
1
Interleave
Mode
Register
Burst Length
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Burst Type
Sequential Interleave
Reserved
Reserved
2
2
4
4
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full page
Reserved
Figure 5: MRS Cycle
/CK
0
1
CK
Command NOP
Precharge
All Banks
2
3
4
5
6
NOP
NOP
tRP * ²
MRS * ¹
NOP
Any
Command
tMR D = 2 tCK
7
NOP
8
NOP
* 1 : MRS can be issued only at all banks precharge state.
* 2 : Minium t_RP is required to issue MRS command.
Doc # 14-02-045 Rev A ECN 01-1118
7
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.