NT5DS4M32EG Datasheet, PDF (19/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
SELF REFRESH
A self refresh command is defined by having /CS, /RAS, /CAS and CKE low with /WE high at the rising edge of the
clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode.
During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh
operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning
CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSR for locking of DLL.
Figure 21: Self Refresh
/CK
CK
Command
CKE
ReSPfeRrelEfsh
All Banks
Self
Refresh
tIS
tXSA ^*1
tXSR ^*2
Active
Rea d
*1 Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after any bank active com-
mand.
*2 Exit self refresh to read command.
POWER DOWN MODE
The power down is entered when CKE Low, and exited when CKE High. Once the power down mode is initiated, all
of the receiver circuits except CK and CKE are gated off to reduce power consumption. All banks should be in idle
state prior to entering the precharge power down mode and CKE should be set high at least 1tCK+tIS prior to Row
active command. During power down mode, refresh operations cannot be performed, therefore the device cannot
remain in power down mode longer than the refresh period (tREF) of the device.
Figure 22: Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
/CK
CK
Command
Precharge
CKE
Precharge
pow er
dow n
Entry
tIS
Precharge
pow er
dow n
Exit
NOP
Active
Active
pow er
dow n
Entry
tIS
tIS
Active
pow er
dow n
Exit
NOP
Rea d
tPDEX
tIS
Doc # 14-02-045 Rev A ECN 01-1118
19
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.