NT5DS4M32EG Datasheet, PDF (15/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
BURST STOP COMMAND
NT5DS4M32EG
Advance Information
The Burst stop command is initiated by having /RAS and /CAS high with /CS and /WE low at the rising edge of the
clock only. The Burst Stop command has the fewest restrictions making it the easiest method to use when
terminating a burst operation before it has been completed. When the Burst Stop command is issued during a burst
read cycle, both the data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the /CAS
Latency set in the Mode Register. The Burst Stop command, however, is not supported during a write burst operation.
Figure 16: Burst Stop Command (Burst Length = 4, /CAS Latency = 3)
/CK
CK
Command
0
1
1t CK
READ
Burst
St op
2
NOP
3
NOP
4
NOP
5
NOP
6
NOP
7
NOP
8
NOP
/CAS Latency = 3
DQS
DQ’s
The burst ends after a delay equal to the /CAS Latency
Dout 0 Dout 1
DM FUNCTION
The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read
cycle. When the Data Mask is activated (DM high) during write operation, the write data is masked immediately (DM to
Data-mask Latency is Zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock
edge.
Figure 17: DM Function (Burst Length = 8)
0
1
2
3
4
5
6
7
8
/CK
CK
Command
DQS
WRITE NOP
tDQSS
tWPREH
NOP
NOP
NOP
NOP
DQ’s
tWPRES
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
NOP
NOP
NOP
DMDM
Mask ed by DM=H
Doc # 14-02-045 Rev A ECN 01-1118
15
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.