NT5DS4M32EG Datasheet, PDF (14/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
Write Interrupted by Precharge & DM
NT5DS4M32EG
Advance Information
A burst Write can be interrupted by a precharge of the same bank before completion of the previous burst. A write
recovery time (tWR) is required from the last data to precharge command. When Precharge command is asserted,
any residual data from the burst write cycle must be masked by DM.
Figure 15: Write Interrupted by Precharge & DM
0
1
2
3
4
5
6
7
8
/CK
CK
Command
DQS
Max tDQ SS
DQ’s
NOP
WRITE A NOP
t DQSSmax
NOP
NOP
NOP
t WR
Precharge _{W RITE B NOP}
t DQSSmax
t WPREH
t WPRES
Din a0 Din a1 Din a2 Din a 3 Din a4 Din a 5 Din a 6 Din a 7
t WPREH
t WPRES
Din a 0 Din a 1
Min tDQSS
DM
DQS
DQ’s
t DQSSmin
t WR
tWPRES
tWPREH
Din a0 Din a1 Din a2 Din a3 Din a4 Din a5 Din a6 Din a 7
t DQSSmin
tWPREH
tWPRES
Din b0 Din b1 Din b2
DM
Doc # 14-02-045 Rev A ECN 01-1118
14
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.