NT5DS4M32EG Datasheet, PDF (25/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
Table 14: Simplified Truth Table
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DM
BA_0,1
A8/AP
A11~A9,
A7~A0
Note
Extended mode
register
H
Register
Mode Register
Set
H
Auto Refresh
H
Entry
Refresh
Self
Refresh _Exit
L
Bank Active & Row Address
H
Auto Precharge
Read &
Disable
Col
H
Addr.
Auto Precharge
Enable
Auto Precharge
Write &
Disable
Col
H
Addr.
Auto Precharge
Enable
Burst Stop
H
Pre-
charge
Bank Selection
All Banks
H
X
L
L
L
L
X
OP CODE
1,2
X
L
L
L
L
X
OP CODE
H
3
L
L
L
H
X
X
L
3
L
H
H
H
3
H
X
X
H
X
X
X
3
X
L
L
H
H
X
V
Row Address
X
L
H
L
H
X
V
L
4
Column
Address
H
4
X
L
H
L
L
X
V
X
L
H
H
L
X
V
X
L
L
H
L
X
X
L
4
Column
Address
H
4,6
X
7
L
X
H
5
HX
X
X
Active Power
Down
Entry
H
L
X
LV
V
V
X
Exit
L
H
XX
X
XX
HX
X
X
Entry
H
L
X
Precharge Power
Down Mode
LH
H
H
X
HX
X
X
Exit
L
H
X
LH
H
H
DM
H
X
V
X
8
HX
X
X
No Operation Command
H
X
X
X
LH
H
H
Note 1. OP CODE : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program Keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycle of EMRS/MRS
3. Auto refresh function are as same as CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A8/AP is “high” at row precharge ,BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges(Write DM latency is 0).
Doc # 14-02-045 Rev A ECN 01-1118
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.