NT5DS4M32EG Datasheet, PDF (13/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
Write Interrupted by Read & DM
NT5DS4M32EG
Advance Information
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at
least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read
command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last
data to read command (tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the
DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write
can not be issued at the next clock edge of the write command.
Figure 14: Write Interrupted by Read & DM (Burst Length = 8)
0
1
2
3
4
5
6
7
8
/CK
CK
Command ^{WRITE NOP}
NOP
NOP
NOP
READ
/CAS
Late nc y=3
DQS
DQ’s
t DQSSmax
t WTR
t WPRES
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
NOP
NOP
NOP
Dout0 Dout1
/CAS
Late nc y=3
DM
DQS
DQ’s
t DQSSmin
t WTR
t WPRES
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
Dout0 Dout1
DM
Doc # 14-02-045 Rev A ECN 01-1118
13
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.