NT5DS4M32EG Datasheet, PDF (20/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
Table 5: Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage Temperature
Power Dissipation
Short circuit current
Symbol
VIN, VOUT
VDD
VDDQ
TSTG
PD
IOS
Value
-0.5~3.6
-1.0~3.6
-0.5~3.6
-55~150
2.0
50
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
V
°C
W
mA
Table 6: Power & DC Operating Condition (SSTL_2 In/Out)
Recommended operating conditions (Voltage referenced to Vss, TA = 0 to 70°C
Parameter
Device Supply Voltage
Output Supply Voltage
Reference Voltage
Termination Voltage
Input Logic High Voltage
Input Logic Low Voltage
Output Logic High Current
Output Logic Low Current
Input Leakage Current
Output Leakage Current
Symbol
V_DD
V_DDQ
V_REF
V_tt
V_IH
V_IL
I_OH
I_OL
I_IL
I_OL
Min
2.375
2.375
0.49*V_DDQ
V_REF-0.04
V_REF+0.15
-0.30
-15.2
15.2
-5
-5
Typ
2.50
2.50
--
V_REF
--
--
--
--
--
--
Max
2.625
2.625
0.51*V_DDQ
V_REF+0.04
V_DDQ+0.30
V_REF-0.15
--
--
5
5
Unit
V
V
V
V
V
V
mA
mA
uA
uA
Note
1
1
2
3
4
5
7
8
6
9
Note :
1. VDD / VDDQ = 2.5V ±5% / 2.5V ±5%
2. VREF is expected to equal 0.50* VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed ± 2% of the DC value. Thus, from 0.50* VDDQ, VREF is allowed ± 25mV for DC error
and an additional ± 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.) = VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.
5. VIL(mim.) =-1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V ≤ VIN ≤ VDD is acceptable. For all other pins that are not under test VIN = 0V.
7. VOH (Output logic high voltage) min = Vtt (min) + 0.76
8. VOL (Output logic low voltage) max = Vtt (max) - 0.76
9. DQs are disabled; 0V ≤ VOUT ≤ VDDQ
Doc # 14-02-045 Rev A ECN 01-1118
20
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.