NT5DS4M32EG Datasheet, PDF (22/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
Table 9: AC Operating Test Conditions
(V_DD = 2.5V±0.125V, TA=0 to 70C)
Parameter
Input Reference voltage for CK (for signal ended)
CK and /CK signal maximum peak swing
CK signal minimum slew rate
Input levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Figure 23: Output Load Circuit
Output O
Z0=50Ω
Value
0.50*V_DDQ
1.5
1.0
V_REF+0.35/V_REF-0.35
V_REF
Vtt
See Figure 23
Vtt=0.5*V_DDQ ^O
R_T=50Ω
n
V _REF
=0 .5*V _DDQ
C_LOAD=20pF
Unit
V
V
V/ns
V
V
V
Note
Table 10: Capacitance (V_DD = 2.5V, TA = 25C, f = 1MHz)
Parameter
Input Capacitance (CK, /CK)
Input Capacitance (A0~A11, BA0~BA1)
Input Capacitance (CKE, /CS, /RAS, /CAS, /WE)
Data & DQS input/output capacitance (DQ0~DQ31)
Input Capacitance (DM0~DM3)
Symbol
Min
CIN1
2.0
CIN2
2.0
CIN3
2.0
COUT
4.0
CIN4
4.0
Max
Unit
3.0
pF
3.0
pF
3.0
pF
5.0
pF
5.0
pF
Table 11: Decoupling Capacitance Guide Line
(Recommended decoupling capacitance added to power line at board)
Parameter
Decoupling Capacitance between VDD and VSS
Decoupling Cpaacitance between VDDQ and VSSQ
Symbol
CDC1
CDC2
Value
0.1+0.01
0.1+0.01
Note :
1. VDD and VDDQ pins are separated from each other.
All VDD pins are connected internally on-chip. All VDDQ pins are connected internally on-chip.
2. VSS and VSSQ pins are separated each other.
All VSS pins are connected internally on-chip. All VSSQ pins are connected internally on-chip.
Unit
µF
µF
Doc # 14-02-045 Rev A ECN 01-1118
22
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.