NT5DS4M32EG Datasheet, PDF (17/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
Write with Auto Precharge
NT5DS4M32EG
Advance Information
If A8 is high when Write command is issued, the write with Auto-Precharge function is performed. Any new command
to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after
keeping tWR (min).
Figure 19: Write with Auto Precharge (Burst Length = 4, /CAS Latency = 3)
0
1
2
3
4
5
6
7
8
/CK
CK
Command
BANK A
AC TIVE
DQS
/CAS Latency = 3
DQ’s
NOP
WRITE A
Auto Prec har ge
NOP
t WPREH
NOP
NOP
NOP
NOP
NOP
t WPRES
Din a0 Din a1 Din a 2 Din a 3
* Bank can be reactiv ated at
completion of t RP
t WR
t RP
Internal precharge starts
Asserted
Command
WRITE
WRITE +
AP
READ
READ +
AP
Active
Precharge
3
Write
No AP
Write
+ AP
Illegal
Illegal
Illegal
Illegal
For Same Bank
4
5
6
7
Write
No AP
Write
+ AP
READ
No AP
+ DM
READ
+ AP
+ DM
Illegal
Illegal
Write
No AP
Write
+ AP
READ
No AP
+ DM
READ
+ AP
+ DM
Illegal
Illegal
Illegal
Illegal
READ
No AP
READ
+ AP
Illegal
Illegal
Illegal
Illegal
READ
No AP
READ
+ AP
Illegal
Illegal
8
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
3
Legal
Legal
Illegal
Illegal
Legal
Legal
For Different Bank
4
5
6
Legal Legal Legal
Legal Legal Legal
Illegal Illegal Legal
Illegal Illegal Legal
Legal
Legal
Legal
Legal
Legal
Legal
7
Legal
Legal
Legal
Legal
Legal
Legal
AP = Auto Precharge
DM : Refer to “Write Interrupted by Read & DM”
Doc # 14-02-045 Rev A ECN 01-1118
17
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.