NT5DS4M32EG Datasheet, PDF (28/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
Table 15: Function Truth Table
Current State /CS /RAS /CAS /WE
Address
H
X
L
H
L
H
L
H
REFRESHING _L
L
L
L
L
L
L
L
X
XX
H
HX
H
LX
L
X BA, CA, A8
H
H BA, RA
H
L BA, A8
L
HX
L
L
Op-Code,
Mode-Add
Command
DESEL
NOP
TERM
READ/WRITE
ACT
PRE/PREA
REFA
MRS
Action
NOP(Idle after tRP)
NOP(Idel after tRP)
NOP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ABBREVIATIONS :
H=High Level, L=Low Level, V=Valid, X=Don’t care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state, May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Same bank’s previous Auto precharge will not be performed. But if Bank is different, previous Auto precharge will be performed.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
Doc # 14-02-045 Rev A ECN 01-1118
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.