NT5DS4M32EG Datasheet, PDF (23/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
.
Table 12: AC Characteristics
Parameter
Symbol
-5G
Min Max
-5
Min Max
-6
Min Max
Unit
Note
CK cycle time
CL=3
CL=2
5.0
12
5.0
12
6.0
12
ns
2,3
9.0 12
--
--
--
--
ns 2,3
CK high level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 tCK
CK low level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS out access time from CK
t_DQSCK -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns
Output Access time from CK
t_AC
-0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns
Data Strobe edge to Dout edge t_DQSQ
-- 0.45 -- 0.45 -- 0.45 ns
1
Read preamble
t_RPRE
0.9
1.1
0.9
1.1
0.9
1.1 tCK
Read postamble
t_RPST
0.4
0.6
0.4
0.6
0.4
0.6 tCK
CK to Valid DQS-in
t_DQSS
0.8
1.2
0.8
1.2
0.8
1.2 tCK
DQS-in setup time
t_WPRES
0
--
0
--
0
--
ns
DQS-in hold time
t_WPREH 0.3
--
0.3
--
0.3
-- tCK
DQS write postamble
t_WPST
0.4
0.6
0.4
0.6
0.4
0.6 tCK
DQS-in high level width
t_DQSH
0.4
0.6
0.4
0.6
0.4
0.6 tCK
DQS-in low level width
t_DQSL
0.4
0.6
0.4
0.6
0.4
0.6 tCK
Address and Control input setup
t_IS
1.0
--
1.0
--
1.0
--
ns
Address and Control input hold
t_IH
1.0
--
1.0
--
1.0
--
ns
DQ and DM setup time to DQS
t_DS
0.45 -- 0.45 -- 0.45 --
ns
DQ and DM hold time to DQS
t_DH
0.45 -- 0.45 -- 0.45 --
ns
Clock half period
t_CL-
t_CL-
t_CL-
MIN
MIN
MIN
t_HP
or
--
or
--
or
--
ns
1
t_CH-
t_CH-
t_CH-
MIN
MIN
MIN
Data output hold time from DQS
t_QH
t_HP
--
t_HP
--
t_HP
--
-0.45
-0.45
-0.45
ns
1
Note 1:
-. The JEDEC DDR specification currently defines the output data valid window (tDV) as the period when the data strobe and all data
associated with that data strobe are coincidentally valid.
-. The previously used definition of tDV(=0.35tDK) artificially penalizes system timing budgets by assuming the worst case output
valid window even then the clock duty cycle applied to the device is better than 45/55%
-. A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and
replaces tDV - tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time (tCH, tCL).
.X=A frequency dependent timing allowance account for tDQSQmax
Note 2
-. For Low frequency operation without DLL (143MHz~83MHz) in CL2/3, need set DLL disable mode for power saving.
-. AC parameters for DLL Disable Mode : Same as “-50” AC parameters except tCK.
Note 3
-. Under set DLL disable mode by EMRS,
-. The tDQSCK can be 0.0ns in 100MHz operation.
-. The tDQSCK can be +3.0ns in 143MHz operation.
-. The tDQSCK can be -2.0ns in 83MHz operation.
Doc # 14-02-045 Rev A ECN 01-1118
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.