NT5DS4M32EG Datasheet, PDF (10/46 Pages) NanoAmp Solutions, Inc. – 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

NanoAmp Solutions, Inc.
Burst Read Operation
NT5DS4M32EG
Advance Information
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the burst read
command is issued by asserting /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock
after tRCD from the bank activation. The address inputs (A0~A7) determine the starting address for the Burst. The
Mode Register sets type of burst (Sequential or interleave) and burst length(2,4,8, Full page). The first output data is
available after the /CAS Latency from the READ command, and the consecutive data are presented on the falling and
rising edge of Data Strobe adopted by DDR SDRAM until the burst length is completed.
Figure 8: Burst Read (Burst Length = 4, /CAS Latency = 3)
0
1
2
3
4
5
6
7
8
/CK
CK
Command
READ
NOP
/CAS Latency = 3
DQS
DQ’s
NOP
NOP
t RPRE
NOP
NOP
t RPST
Dout 0 Dout 1 Dout 2 Dout 3
NOP
NOP
NOP
Burst Write Operation
The Burst Write command is issued by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of
the clock. The address inputs determine the starting column address. There is no real write latency required for burst
write cycle. The first data for burst write cycle must be applied at the first rising edge of the data strobe enabled after
tDQSS from the rising edge of the clock that the write command is issued.The remaining data inputs must be supplied
on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has
been finished, any additional data supplied to the DQ pins will be ignored.
Figure 9: Burst Write (Burst Length = 4)
0
1
2
3
4
5
6
7
8
/CK
CK
Command
DQS
DQ’s
NOP
WRITEA NOP
t DQSSmax
t WPREH
W RIT EB
NOP
NOP
NOP
t WPST
t WPRES
Din a0 Din a1 Din a 2 Din a3 Din b0 Din b1 Din b2 Din b3
NOP
NOP
Doc # 14-02-045 Rev A ECN 01-1118
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.