MC68HC705P6A Datasheet, PDF (98/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Central Processor Unit (CPU) Core
12.3.5 Condition Code Register
The CCR shown in Figure 12-1 is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed. The fifth bit
is the interrupt mask. These bits can be individually tested by a program,
and specific actions can be taken as a result of their state. The condition
code register should be thought of as having three additional upper bits
that are always ones. Only the interrupt mask is affected by a reset of the
device. The following paragraphs explain the functions of the lower five
bits of the condition code register.
H — Half Carry Bit
When the half-carry bit is set, it means that a carry occurred between
bits 3 and 4 of the accumulator during the last ADD or ADC (add with
carry) operation. The half-carry bit is required for binary-coded
decimal (BCD) arithmetic operations.
I — Interrupt Mask Bit
When the interrupt mask is set, the internal and external interrupts are
disabled. Interrupts are enabled when the interrupt mask is cleared.
When an interrupt occurs, the interrupt mask is automatically set after
the CPU registers are saved on the stack, but before the interrupt
vector is fetched. If an interrupt request occurs while the interrupt
mask is set, the interrupt request is latched. Normally, the interrupt is
processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its state before the interrupt
was encountered. After any reset, the interrupt mask is set and can
only be cleared by the clear I bit (CLI), STOP, or WAIT instructions.
N — Negative Bit
The negative bit is set when the result of the last arithmetic operation,
logical operation, or data manipulation was negative. (Bit 7 of the
result was a logic one.)
The negative bit can also be used to check an often-tested flag by
assigning the flag to bit 7 of a register or memory location. Loading
the accumulator with the contents of that register or location then sets
or clears the negative bit according to the state of the flag.
Advance Information
98
Central Processor Unit (CPU) Core
MC68HC705P6A — Rev. 2.0
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