MC68HC705P6A Datasheet, PDF (60/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Input/Output Port (SIOP)
HCO5 INTERNAL BUS
SPE
76543210
CONTROL
REGISTER
$0A
BAUD
RATE
GENERATOR
76543210
STATUS
REGISTER
$0B
76543210
8-BIT
SDO
SHIFT
REGISTER
SDI
$0C
I/O
CONTROL
LOGIC
SCK
INTERNAL
CPU CLOCK
Figure 7-1. SIOP Block Diagram
SDO/PB5
SDI/PB6
SCK/PB7
7.3 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave
operation. No external mode selection inputs are available (for instance,
slave select pin).
7.3.1 Serial Clock (SCK)
The state of the SCK output normally remains a logic 1 during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time, the first bit of received data may
be presented at the SDI pin and the first bit of transmitted data is
presented at the SDO pin (see Figure 7-2). Data is captured at the SDI
pin on the rising edge of SCK. The transfer is terminated upon the eighth
rising edge of SCK.
The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is dependent upon the SPR0 and SPR1 bits located
in the mask option register. Refer to 11.3 Mask Option Register for a
description of available SCK frequencies.
Advance Information
60
Serial Input/Output Port (SIOP)
MC68HC705P6A — Rev. 2.0
MOTOROLA