MC68HC705P6A Datasheet, PDF (46/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Interrupts
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear) and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The SWI is executed the
same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$1FF8 through $1FFF. If more than one interrupt is pending when the
interrupt vector is fetched, the interrupt with the highest vector location
shown in Table 5-1 will be serviced first.
Table 5-1. Vector Addresses for Interrupts and Reset
Register
N/A
N/A
N/A
TSR
TSR
TSR
Flag
Name
Interrupts
N/A Reset
N/A Software
N/A External Interrupt
ICF Timer Input Capture
OCF Timer Output Compare
TOF Timer Overflow
CPU
Interrupt
RESET
SWI
IRQ
TIMER
TIMER
TIMER
Vector
Address
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF8–$1FF9
An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the CPU state to be
recovered from the stack and normal processing to resume at the next
instruction that was to be executed when the interrupt took place.
Figure 5-1 shows the sequence of events that occurs during interrupt
processing.
Advance Information
46
Interrupts
MC68HC705P6A — Rev. 2.0
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