MC68HC705P6A Datasheet, PDF (92/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Mask Option Register (MOR)
Address: $1EFF
Bit 7
Read:
PA7PU
Write:
Erased State: 0
6
PA6PU
0
5
PA5PU
0
4
PA4PU
0
3
PA3PU
0
2
PA2PU
0
1
PA1PU
0
Bit 0
PA0PU
0
Address: $1F00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SECURE
Write:
SWAIT SPR1 SPR0 LSBF LEVEL COP
Erased State: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-1. Mask Option Register (MOR)
COP — COP Watchdog Enable
Setting the COP bit will enable the COP watchdog timer. The COP will
reset the MCU if the timeout period is reached before the COP
watchdog timer is cleared by the application software and the voltage
applied to the IRQ/V_PP pin is between V_SS and V_DD. Clearing the
COP bit will disable the COP watchdog timer regardless of the voltage
applied to the IRQ/V_PP pin.
LEVEL — IRQ Edge Sensitivity
If the LEVEL bit is clear, the IRQ/V_PP pin will only be sensitive to the
falling edge of the signal applied to the IRQ/V_PP pin. If the LEVEL bit
is set, the IRQ/V_PP pin will be sensitive to both the falling edge of the
input signal and the logic low level of the input signal on the IRQ/V_PP
pin.
LSBF — SIOP Least Significant Bit First
If the LSBF bit is set, the serial data to and from the SIOP will be
transferred least significant bit first. If the LSBF bit is clear, the serial
data to and from the SIOP will be transferred most significant bit first.
Advance Information
92
Mask Option Register (MOR)
MC68HC705P6A — Rev. 2.0
MOTOROLA