MC68HC705P6A Datasheet, PDF (71/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Capture/Compare Timer
Timer I/O Registers
8.4.3 Timer Registers
The timer registers (TRH and TRL), shown in Figure 8-4, contains the
current high and low bytes of the 16-bit counter. Reading TRH before
reading TRL causes TRL to be latched until TRL is read. Reading TRL
after reading the timer status register clears the timer overflow flag
(TOF). Writing to the timer registers has no effect.
Address: TRH — $0018
Bit 7
6
Read: TRH7 TRH6
Write
Reset: 1
1
5
TRH5
1
4
TRH4
1
3
TRH3
1
2
TRH2
1
1
TRH1
1
Bit 0
TRH0
1
Address: TRL — $0019
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-4. Timer Registers (TRH and TRL)
MC68HC705P6A — Rev. 2.0
MOTOROLA
Capture/Compare Timer
Advance Information
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